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EM78P258N
8-Bit Microprocessor with OTP ROM
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
June 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 308 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel:+41 43 299-4060 Fax:+41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
Contents
Contents
1 2 3 4 5 6 General Description ...................................................................................... 1 Features ......................................................................................................... 1 Pin Configurations (Package) ...................................................................... 2
3.1 EM78P258NP/N Pin Assignments ..................................................................... 2
Functional Block Diagram ............................................................................ 3 Pin Descriptions ............................................................................................ 4
5.1 6.1 EM78P258NP/N Pin Description........................................................................ 4 Operational Registers......................................................................................... 5
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 R0 (Indirect Address Register) ...........................................................................5 R1 (Time Clock /Counter)....................................................................................5 R2 (Program Counter) and Stack........................................................................5 6.1.3.1 Data Memory Configuration .................................................................7 R3 (Status Register) ............................................................................................8 R4 (RAM Select Register)...................................................................................8 R5 ~ R6 (Port 5 ~ Port 6) ....................................................................................9 R7 (Port 7)...........................................................................................................9 R8 (AISR: ADC Input Select Register) ..............................................................10 R9 (ADCON: ADC Control Register).................................................................11 RA (ADOC: ADC Offset Calibration Register) ...................................................12 RB (ADDATA: Converted Value of ADC)...........................................................12 RC (ADDATA1H: Converted Value of ADC)......................................................13 RD (ADDATA1L: Converted Value of ADC) ......................................................13 RE (Interrupt Status 2 & Wake-Up Control Register) ........................................13 RF (Interrupt Status 2 Register) ........................................................................14 R10 ~ R3F .........................................................................................................14 A (Accumulator).................................................................................................15 CONT (Control Register)...................................................................................15 IOC50 ~ IOC70 (I/O Port Control Register) ......................................................16 IOC80 (TCCA Control Register)........................................................................16 IOC90 (TCCB and TCCC Control Register)......................................................17 IOCA0 (IR and TCCC Scale Control Register) .................................................17 IOCB0 (Pull-Down Control Register).................................................................19 IOCC0 (Open-Drain Control Register) ..............................................................19 IOCD0 (Pull-high Control Register)...................................................................20 IOCE0 (WDT Control & Interrupt Mask Registers 2) ........................................20 IOCF0 (Interrupt Mask Register).......................................................................21 IOC51 (TCCA Counter) .....................................................................................22
* iii
Function Description..................................................................................... 5
6.2
Special Purpose Registers ............................................................................... 15
6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 6.2.12
Product Specification (V1.0) 06.16.2005
Contents
6.2.13 6.2.14 6.2.15 6.2.16 6.2.17 6.2.18 6.2.19
IOC61 (TCCB Counter) .....................................................................................22 IOC71 (TCCBH / MSB Counter) .......................................................................22 IOC81 (TCCC Counter).....................................................................................23 IOC91 (Low-Time Register) ..............................................................................23 IOCA1 (High Time Register) .............................................................................24 IOCB1 High/Low Time Scale Control Register) ................................................24 IOCC1 (TCC Prescaler Counter) ......................................................................25
6.3 6.4 6.5
TCC/WDT and Prescaler.................................................................................. 25 I/O Ports ........................................................................................................... 26
6.4.1 6.5.1 Usage of Port 5 Input Change Wake-up/Interrupt Function..............................29 RESET and Wake-up Operation .......................................................................29 6.5.1.1 Wake-Up and Interrupt Modes Operation Summary..........................32 6.5.1.2 Register Initial Values after Reset ......................................................34 6.5.1.3 Controller Reset Block Diagram.........................................................38 The T and P Status under STATUS (R3) Register ............................................39
RESET and Wake-up ....................................................................................... 29
6.5.2
6.6 6.7
Interrupt ............................................................................................................ 39 Analog-To-Digital Converter (ADC) .................................................................. 42
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA) ...............................42 6.7.1.1 R8 (AISR: ADC Input Select Register) ...............................................42 6.7.1.2 R9 (ADCON: AD Control Register) ....................................................43 6.7.1.3 RA (ADOC: AD Offset Calibration Register).......................................44 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD) ...............45 ADC Sampling Time ..........................................................................................45 AD Conversion Time .........................................................................................45 ADC Operation during Sleep Mode...................................................................45 Programming Process/Considerations..............................................................46 6.7.6.1 Programming Process........................................................................46 6.7.6.2 Sample Demo Programs ....................................................................47 Overview ...........................................................................................................49 Function Description..........................................................................................50 Programming the Related Registers ................................................................52 Overview ...........................................................................................................53 Function Description..........................................................................................53 Programming the Related Registers .................................................................55 Oscillator Modes................................................................................................55 Crystal Oscillator/Ceramic Resonators (XTAL) .................................................56 External RC Oscillator Mode.............................................................................58 Internal RC Oscillator Mode ..............................................................................59
6.7.2 6.7.3 6.7.4 6.7.5 6.7.6
6.8
Infrared Remote Control Application/PWM Waveform Generation................... 49
6.8.1 6.8.2 6.8.3
6.9
Timer / Counter................................................................................................. 53
6.9.1 6.9.2 6.9.3 6.10.1 6.10.2 6.10.3 6.10.4
6.10 Oscillator .......................................................................................................... 55
iv *
Product Specification (V1.0) 06.16.2005
Contents
6.11 Power-on Considerations ................................................................................. 59
6.11.1 Programmable WDT Time-Out Period ..............................................................60 6.11.2 External Power-on Reset Circuit .......................................................................60 6.11.3 Residual Voltage Protection ..............................................................................60
6.12 Code Option ..................................................................................................... 62
6.12.1 Code Option Register (Word 0).........................................................................62 6.12.2 Code Option Register (Word 1).........................................................................63 6.12.3 Customer ID Register (Word 2).........................................................................64
6.13 Instruction Set .................................................................................................. 64
7 8
Absolute Maximum Ratings ....................................................................... 66 DC Electrical Characteristics ..................................................................... 67
8.1 8.2 AD Converter Characteristics........................................................................... 68 Device Characteristics...................................................................................... 69
9 AC Electrical Characteristic ....................................................................... 70 10 Timing Diagrams ......................................................................................... 71
APPENDIX A. Package Types Summary ........................................................................... 72 B Packaging Configurations .......................................................................... 72
B.1 14-Lead Plastic Dual in line (PDIP) -- 300 mil ................................................. 72 B.2 14-Lead Plastic Small Outline (SOP) -- 150 mil .............................................. 73
C
Quality Assurance and Reliability.............................................................. 74
C.1 Address Trap Detect......................................................................................... 74
Product Specification (V1.0) 06.16.2005
*v
Contents
Specification Revision History
Doc. Version 1.0 Revision Description Initial official version Date 2005/06/16
vi *
Product Specification (V1.0) 06.16.2005
EM78P258N
8-Bit Microprocessor with OTP ROM
1
General Description
EM78P258N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. It is equipped with a 2K*13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). With its OTP-ROM feature, it is able to offer a convenient way of developing and verifying your programs. Moreover, it provides a protect bit to guard against code intrusion, as well as 3 Code Option words to accommodate your requirements. Furthermore you can take advantage of ELAN Writer to easily write your development code into the EM78P258N.
2
Features
Operating voltage range:2.3V~5.5V 2.5V~5.5V base on 0C ~ 70C (commercial) base on -40C ~ 85C (industrial)
Operating frequency range (base on 2 clocks):
* Crystal mode: DC ~ 20MHz/2clks, 5V; DC ~ 8MHz/2clks, 3V * RC mode: DC ~ 4MHz/2clks, 5V; DC ~ 4MHz/2clks, 3V
Low power consumption:
* Less than 1.9 mA at 5V/4MHz * Typically 15 A, at 3V/32KHz * Typically 1 A, during sleep mode
Built-in RC oscillator 4MHz, 8MHz,1MHz, 455KHz (auto calibration) Programmable WDT time (4.5ms:18ms) Independent Programmable prescaler of WDT One configuration register to match your requirements, and user's ID code for customer use is provided 80x 8 on chip registers (SRAM, general purpose register) 2K x 13 on chip ROM Bi-directional I/O ports 8-level stacks for subroutine nesting 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt 8-bit real time clock/counter (TCCA, TCCC) and 16-bit real time clock/counter (TCCB) with selective signal sources, trigger edges, and overflow interrupt 4-bit multi-channel Analog-to-Digital Converter with 12-bit resolution Easy-implemented IR (Infrared remote control) application circuit
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
*1
EM78P258N
8-Bit Microprocessor with OTP ROM Power down (SLEEP) mode Five interrupt sources:
* * * * *
TCC, TCCA, TCCB, and TCCC overflow interrupt Input-port status change interrupt (wake-up from sleep mode) External interrupt IR/PWM interrupt ADC completion interrupt
Programmable free running watchdog timer 8 programmable pull-high I/O pins 8 programmable open-drain I/O pins 8 programmable pull-down I/O pins. Two or Four clocks per instruction cycle Package types:
* 14 pin DIP 300mil : EM78P258NP * 14 pin SOP 150mil : EM78P258NN
Power on voltage detector available (2.0V 0.1V)
3
Pin Configurations (Package)
3.1 EM78P258NP/N Pin Assignments
P52/ADC2 P53/ADC3 P54/TCC/VREF /RESET Vss P60//INT P61/TCCA 1 2 3 4 5 6 7 EM78P258NP EM78P258NN 14 13 12 11 10 9 8 P51/ADC1 P50/ADC0 P55/OSCI P70/OSCO VDD P67/IR OUT P66/CIN-
Fig. 3-1 Pin Assignment - EM78P258NP/N
2*
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
4
Functional Block Diagram
WDT timer
TCC
/INT
ROM
R2
STACK 0 STACK 1 STACK 2 STACK 3
OSCI
OSCO /RESET
Oscillator Timing
STACK 4
Control
Prescaler
STACK 5
Interrupt controller
RAM
Built-in OSC
R1(TCC)
Instruction
Register
STACK 6
STACK 7
ALU
R4
Instruction decoder
R3
ACC
DATA & CONTROL BUS
IOC5
COUNTER
IOC6/7
PORT5
R5
R6/7
Fig. 4-1 EM78P258N Functional Block Diagram
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
*3
EM78P258N
8-Bit Microprocessor with OTP ROM
5
Pin Descriptions
5.1
VDD OSCI
EM78P258NP/N Pin Description
Pin No.
10 12
Symbol
Type
- I Power supply
Function
XTAL type Crystal input terminal or external clock input pin RC type: RC oscillator input pin XTAL type: Output terminal for crystal oscillator or external clock input pin RC type: Clock output with a duration one instruction cycle External clock signal input
OSCO
11
I/O
P70 P60, P61 P66, P67
11
I/O
General-purpose I/O pin Default value at power-on reset General-purpose I/O pin Open_drain Default value at power-on reset General-purpose I/O pin
6~9
I/O
P50 ~ P55
1~3 12 ~ 14
I/O
Pull_high/pull_down Wake up from sleep mode when the status of the pin changes Default value at power-on reset IR mode output pin. Driving current = 10mA when the output voltage drops to
IR OUT
13
O
Vdd-0.5V at Vdd = 5V Sinking current = 15mA when the output voltage drops to GND+0.5V at Vdd = 5V
External reference voltage for ADC Defined by ADCON (R9)<7> External interrupt pin triggered by falling or rising edge Defined by CONT <7> External Counter input
VREF /INT TCC, TCCA,
3 6 3, 7,
I I
I 1, 2, 13, 14
TCC defined by CONT<5> TCCA defined by IOC80 <1> Analog to Digital Converter Defined by ADCON (R9)<1:0> If it remains at logic low, the device will be reset Wake-up from sleep mode when pin status changes Voltage on /RESET/Vpp must not exceed Vdd during normal mode Ground.
ADC0 ~ ADC3
I
/RESET
4
I
VSS
5
-
4*
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6
Function Description
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4).
6.1.2 R1 (Time Clock /Counter)
Increased by an external signal edge which is defined by the TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. Writable and readable as any other registers The TCC prescaler counter (IOCC1) is assigned to TCC The contents of the IOCC1 register is cleared whenever - * a value is written to TCC register. * a value is written to TCC prescaler bits (Bit3, 2, 1, 0 of the CONT register) * during power on reset, /RESET, or WDT time out reset.
6.1.3 R2 (Program Counter) and Stack
R3
Reset Vector Hardware Interrupt Vector
A10
A9 A8
A7 CALL RET RETL RETI
~
A0
User Memory Space
00 PAGE0 0000~03FF 01 PAGE1 0400~07FF
Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 Stack Level 6 Stack Level 7 Stack Level 8
On-chip Program Memory
Fig. 6-1 Program Counter Organization
R2 and hardware stacks are 12-bit wide. The structure is depicted in the table under Section 6.1.3.1, Data Memory Configuration (next page). Generates 2Kx13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. The contents of R2 are all set to "0"s when a RESET condition occurs.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
*5
EM78P258N
8-Bit Microprocessor with OTP ROM "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged. Any instruction (except "ADD R2,A") that is written to R2 (e.g., "MOV R2, A", "BC R2, 6",) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged. In the case of EM78P258N, the most significant bit (A10) will be loaded with the content of PS0 in the status register (R3) upon execution of a "JMP", "CALL", or any other instructions set which write to R2. All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instructions that are written to R2. Note that these instructions need one or two instructions cycle as determined by Code Option Register CYES bit.
6*
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM 6.1.3.1 Data Memory Configuration
Address R PAGE registers IOCX0 PAGE registers IOCX1 PAGE registers
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF
(Indirect Addressing Register) (Time Clock Counter) (Program Counter) (Status Register) (RAM Select Register) (Port5) (Port6) (Port7) (ADC Input Select Register (ADC Control Register) (ADC Offset Calibration Register) (The converted value AD11~AD4 of ADC) (The converted value AD11~AD8 of ADC) (The converted value AD7~AD0 of ADC) (Interrupt Status 2 and Wake-Up Control Register (Interrupt Status Register 1)
Reserve CONT (Control Register) Reserve Reserve Reserve IOC50 (I/O Port Control Register) IOC60 (I/O Port Control Register) IOC70 (I/O Port Control Register) IOC80 (TCCA Control Register) (TCCB and TCCC Control Register) (IR and TCCC Scale IOCA0 Control Register) IOC90 IOCB0 (Pull-down Control Register) IOCC0 (Open-drain Control Register) IOCD0 (Pull-high Control Register) IOCE0 (WDT Control Register and Interrupt Mask Register 2) IOCF0 (Interrupt Mask Register 1) IOC51 IOC61 IOC71 IOC81 IOC91 IOCA1 IOCB1 IOCC1
Reserve Reserve Reserve Reserve Reserve (TCCA Counter) (TCCB LSB Counter) (TCCB HSB Counter) (TCCC Counter) (Low-Time Register) (High-Time Register) (High-Time and Low-Time Scale control Register) (TCC Prescaler Control) Reserve Reserve Reserve
General Registers 1F 20 3F
Bank0
Bank1
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
*7
EM78P258N
8-Bit Microprocessor with OTP ROM
6.1.4 R3 (Status Register)
7
RST
6
IOCS
5
PS0
4
T
3
P
2
Z
1
DC
0
C
Bit 7 (RST): Bit of reset type Set to "1" if wake-up from sleep on pin change, status change, or AD conversion completed. Set to "0" if wake-up from other reset types Bit 6 (IOCS): Select the Segment of IO control register 0 = Segment 0 (IOC50 ~ IOCF0) selected 1 = Segment 1 (IOC51 ~ IOCC1) selected Bit 5 (PS0): Page select bits. PS0 is used to select a program memory page. When executing a "JMP," "CALL," or other instructions which cause the program counter to change (e.g., MOV R2, A), PS0 is loaded into the 11th bit of the program counter where it selects one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0 bit. That is, the return will always be back to the page from where the subroutine was called, regardless of the current PS0 bit setting. PS0
0 1
Program Memory Page [Address]
Page 0 [000-3FF] Page 1 [400-7FF]
Bit 4 (T): Bit 3 (P): Bit 2 (Z): Bit 1 (DC): Bit 0 (C):
Time-out bit. Set to "1" by the "SLEP" and "WDTC" commands, or during power on and reset to "0" by WDT time-out. Power-down bit. Set to "1" during power-on or by a "WDTC" command and reset to "0" by a "SLEP" command. Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Auxiliary carry flag Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7: Bit 6: Bits 5~0: Set to "0" all the time Used to select Bank 0 or Bank 1 of register Used to select a register (address: 00~0F, 10~3F) in the indirect addressing mode
See the table under Section 6.1.3.1, Data Memory Configuration for the configuration of the data memory.
8*
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 & R6 are I/O registers The upper 2 bits of R5 are fixed to "0" Only the lower 6 bits of R5 are available The Bit2 ~ Bit5 of R6 are fixed to"0" Only Bits 1, 2, 6 and, 7 of R6 are available
6.1.7 R7 (Port 7)
Bit
EM78P258N ICE259N
7
`0' C3
6
`0' C2
5
`0' C1
4
`0' C0
3
`0' RCM1
2
`0' RCM0
1
`0' `0'
0
I/O I/O
NOTE R7 is I/O registers With EM78P258N, only the lower 1 bit of R7 is available.
Bit 7 ~ Bit 2: [With EM78P258N]: Unimplemented, read as `0'.
[With Simulator (C3~C0, RCM1, & RCM0)]: are IRC calibration bits in IRC oscillator mode. Under IRC oscillator mode of ICE255N (with ICE259N) (simulator, these are the IRC mode selection bits and IRC calibration bits. Bit 7 ~ Bit 4 (C3 ~ C0): Calibrator of internal RC mode
C3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
C2
0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
C1
0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0
C0
0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0
Frequency (MHz)
(1-36%) x F (1-31.5%) x F (1-27%) x F (1-22.5%) x F (1-18%) x F (1-13.5%) x F (1-9%) x F (1-4.5%) x F F (default) (1+4.5%) x F (1+9%) x F (1+135%) x F (1+18%) x F (1+22.5%) x F (1+27%) x F (1+31.5%) x F
NOTE: 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode. Hence, they are shown for reference only. Definite values will depend on the actual process. 2. Similar way of calculation is also applicable to low frequency mode.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
*9
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 3 & Bit 2 ( RCM1, RCM0): IRC mode selection bits
RCM 1 1 1 0 0 RCM 0 1 0 1 0 Frequency (MHz) 4 (default) 8 1 455kHz
6.1.8 R8 (AISR: ADC Input Select Register)
The AISR register defines the pins of Port 5 as analog inputs or as digital I/O, individually. 7
-
6
-
5
-
4
-
3
ADE3
2
ADE2
1
ADE1
0
ADE0
Bit 7 ~ Bit 4:
Not used
Bit 3 (ADE3 ): AD converter enable bit of P53 pin 0 = Disable ADC3, P53 acts as I/O pin 1 = Enable ADC3, acts as analog input pin Bit 2 (ADE2 ): AD converter enable bit of P52 pin 0 = Disable ADC2, P52 acts as I/O pin 1 = Enable ADC2, acts as analog input pin Bit 1 (ADE1 ): AD converter enable bit of P51 pin 0 = Disable ADC1, P51 acts as I/O pin 1 = Enable ADC1, acts as analog input pin Bit 0 (ADE0 ): AD converter enable bit of P50 pin. 0 = Disable ADC0, P50 acts as I/O pin 1 = Enable ADC0, acts as analog input pin
10 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.1.9 R9 (ADCON: ADC Control Register)
7
VREFS
6
CKR1
5
CKR0
4
ADRUN
3
ADPD
2
-
1
ADIS1
0
ADIS0
Bit 7 (VREFS): The input source of the Vref of the ADC 0 = The Vref of the ADC is connected to Vdd (default value), and the P54/VREF pin carries out the function of P54 1 = The Vref of the ADC is connected to P54/VREF
NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If P53/TCC/VREF acts as VREF analog input pin, then CONT Bit 5 "TS" must be "0." The P54/TCC/VREF pin priority is as follows: P53/TCC/VREF Pin Priority High VREF Medium TCC Low P54
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of oscillator clock rate of ADC 00 = 1: 4 (default value) 01 = 1: 16 10 = 1: 64 11 = 1: WDT ring oscillator frequency
CKR0:CKR1 00 01 10 11 Operation Mode Fsco/4 Fsco/16 Fsco/64 Internal RC Max. Operation Frequency 1 MHz 4 MHz 16MHz 1 MHz
Bit 4 (ADRUN): ADC starts to RUN. 1 = an AD conversion is started. This bit can be set by software 0 = Reset upon completion of the conversion. This bit cannot be reset through software Bit 3 (ADPD): ADC Power-down mode 1 = ADC is operating 0 = Switch off the resistor reference to save power even while the CPU is operating Bit 2: Not used
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 11
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 1 ~ Bit 0 (ADIS1 ~ADIS0): Analog Input Select 00 = ADIN0/P50 01 = ADIN1/P51 10 = ADIN2/P52 11 = ADIN3/P53 These bits can only be changed when the ADIF bit (see Section 6.1.14, RE (Interrupt Status 2 & Wake-Up Control Register)) and the ADRUN bit are both LOW.
6.1.10 RA (ADOC: ADC Offset Calibration Register)
7
CALI
6
SIGN
5
VOF[2]
4
VOF[1]
3
VOF[0]
2
"0"
1
"0"
0
"0"
Bit 7 (CALI):
Calibration enable bit for ADC offset 0 = Calibration disable 1 = Calibration enable
Bit 6 (SIGN):
Polarity bit of offset voltage 0 = Negative voltage 1 = Positive voltage
Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits VOF[2] VOF[1] VOF[0] EM78P258N
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB
ICE259N
0LSB 1LSB 2LSB 3LSB 4LSB 5LSB 6LSB 7LSB
Bit 2 ~ Bit 0:
Unimplemented, read as `0'
6.1.11 RB (ADDATA: Converted Value of ADC)
7
AD11
6
AD10
5
AD9
4
AD8
3
AD7
2
AD6
1
AD5
0
AD4
When the AD conversion is completed, the result is loaded into the ADDATA. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-Up Control Register)) is set. RB is read only.
12 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.1.12 RC (ADDATA1H: Converted Value of ADC)
7
"0"
6
"0"
5
"0"
4
"0"
3
AD11
2
AD10
1
AD9
0
AD8
When the AD conversion is completed, the result is loaded into the ADDATA1H. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-Up Control Register)) is set. RC is read only
6.1.13 RD (ADDATA1L: Converted Value of ADC)
7
AD7
6
AD6
5
AD5
4
AD4
3
AD3
2
AD2
1
AD1
0
AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 & Wake-Up Control Register)) is set. RD is read only
6.1.14
7
-
RE (Interrupt Status 2 & Wake-Up Control Register)
6
-
5
ADIF
4
-
3
ADWE
2
-
1
ICWE
0
-
NOTE RE <5> can be cleared by instruction but cannot be set. IOCE0 is the interrupt mask register. Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 & Bit 6: Bit 5 (ADIF):
Not used Interrupt flag for analog to digital conversion. Set when AD conversion is completed. Reset by software 0 = no interrupt occurs 1 = interrupt request
Bit 4 : Bit 3 (ADWE):
Not used, fixed to "0" ADC wake-up enable bit 0 = Disable ADC wake-up 1 = Enable ADC wake-up When AD Conversion enters sleep mode, this bit must be set to "Enable."
Bit 2 (CMPWE): Not used, fixed to "0"
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 13
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 1 (ICWE): Port 5 input change to wake-up status enable bit 0 = Disable Port 5 input change to wake-up status 1 = Enable Port 5 input change to wake-up status When Port 5 change enters sleep mode, this bit must be set to "Enable." Bit 0: Not implemented, read as `0'
6.1.15
7
LPWTIF
RF (Interrupt Status 2 Register)
6
HPWTIF
5
TCCCIF
4
TCCBIF
3
TCCAIF
2
EXIF
1
ICIF
0
TCIF
NOTE "1" means interrupt request; "0" means no interrupt occurs. RF can be cleared by instruction but cannot be set. IOCF0 is the relative interrupt mask register. Reading RF will result to "logic AND" of RF and IOCF0.
Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM function. Reset by software. Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM function. Reset by software. Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by software. Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCC overflows. Reset by software. Bit 3 (TCCAIF): TCCA overflow interrupt flag. Set when TCCC overflows. Reset by software. Bit 2 (EXIF): Bit 1 (ICIF): Bit 0 (TCIF): External interrupt flag. Set by falling edge on /INT pin. Reset by software. Port 5 input status change interrupt flag. Set when Port 5 input changes. Reset by software. TCC overflow interrupt flag. Set when TCC overflows. Reset by software.
6.1.16 R10 ~ R3F
These are all 8-bit general-purpose registers.
14 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.2
Special Purpose Registers
6.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding. It cannot be addressed.
6.2.2 CONT (Control Register)
7
INTE
6
INT
5
TS
4
TE
3
PSTE
2
PST2
1
PST1
0
PST0
NOTE The CONT register is both readable and writable. Bit 6 is read only.
Bit 7 (INTE): INT signal edge 0 = interrupt occurs at the rising edge on the INT pin 1 = interrupt occurs at the falling edge on the INT pin Bit 6 (INT): Interrupt enable flag 0 = masked by DISI or hardware interrupt 1 = enabled by the ENI/RETI instructions This bit is readable only. Bit 5 (TS): TCC signal source 0 = internal instruction cycle clock. P54 is bi-directional I/O pin. 1 = transition on the TCC pin Bit 4 (TE): TCC signal edge 0 = increment if the transition from low to high takes place on the TCC pin 1 = increment if the transition from high to low takes place on the TCC pin. Bit 3 (PSTE): Prescaler enable bit for TCC 0 = prescaler disable bit. TCC rate is 1:1. 1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0. Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits PST2
0 0 0 0 1 1 1 1 Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
PST1
0 0 1 1 0 0 1 1
PST0
0 1 0 1 0 1 0 1
TCC Rate
1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 * 15
EM78P258N
8-Bit Microprocessor with OTP ROM
NOTE Tcc timeout period [1/Fosc x prescaler x 256(Tcc cnt) x 1(CLK=2)] Tcc timeout period [1/Fosc x prescaler x 256(Tcc cnt) x 2(CLK=4)]
6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
"1" puts the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. Only the lower 6 bits of IOC50 can be defined. Only the bit1, 2, 6 and, 7 of IOC60 can be defined. Only the lower 1 bits of IOC70 can be defined, the others bits are not available. IOC50, IOC60, and IOC70 registers are all readable and writable
6.2.4 IOC80 (TCCA Control Register)
7
-
6
-
5
-
4
-
3
-
2
TCCAEN
1
TCCATS
0
TCCATE
NOTE Bit4 ~ 0 of IOC80 register is both readable and writable. Bit5 of IOC80 register is readable only.
Bit 7 ~ Bit 5: Bit 4 & Bit 3: Bit 2 (TCCAEN):
Not used Not used, fixed to "0". TCCA enable bit 0 = disable TCCA 1 = enable TCCA as a counter
Bit 1 (TCCATS):
TCCA signal source 0 =: internal instruction cycle clock. P61 is a bi-directional I/O pin. 1 = transit through the TCCA pin
Bit 0 (TCCATE):
TCCA signal edge 0 = increment if transition from low to high takes place on the TCCA pin 1 = increment if transition from high to low takes place on the TCCA pin
16 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.2.5 IOC90 (TCCB and TCCC Control Register)
7
TCCBHE
6
TCCBEN
5
-
4
-
3
-
2
TCCCEN
1
-
0
-
Bit 7 (TCCBHE): Control bit is used to enable the most significant byte of counter 1 = Enable the most significant byte of TCCBH TCCB is a 16-bit counter 0 = Disable the most significant byte of TCCBH (default value) TCCB is an 8-bit counter Bit 6 (TCCBEN): TCCB enable bit 0 = disable TCCB 1 = enable TCCB as a counter Bit 5 & Bit 4: Bit 3: Not used, fixed to "0". Not used.
Bit 2 (TCCCEN): TCCC enable bit 0 = disable TCCC 1 = enable TCCC as a counter Bit 1 & Bit 0: Not used, fixed to "0".
6.2.6 IOCA0 (IR and TCCC Scale Control Register)
7
TCCCSE
6
TCCCS2
5
TCCCS1
4
TCCCS0
3
IRE
2
HF
1
LGP
0
IROUTE
Bit 7 (TCCCSE): Scale enable bit for TCCC An 8-bit counter is provided as scale for TCCC and IR-Mode. When in IR-Mode, TCCC counter scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description). 0 = scale disable bit, TCCC rate is 1:1 1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 17
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to determine the scale ratio of TCCC as shown below:
TCCCS2 0 0 0 0 1 1 1 1 TCCCS1 0 0 1 1 0 0 1 1 TCCCS0 0 1 0 1 0 1 0 1 TCCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (IRE):
Infrared Remote Enable bit 0 = Disable IRE, i.e., disable H/W Modulator Function. IROUT pin fixed to high level and the TCCC is UP Counter. 1 = Enable IRE, i.e., enable H/W Modulator Function. Pin 67 defined as IROUT. If HP=1, the TCCC counter scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description). When HP=0, the TCCC is UP Counter.
Bit 2 (HF):
High Frequency bit 0 = PWM application. IROUT waveform is achieved according to high-pulse width timer and low-pulse width timer which determine the high time width and low time width respectively 1 = IR application mode. The low-time segments of the pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description)
Bit 1 (LGP):
Long Pulse. 0 = The high-time register and low-time register is valid 1 = The high-time register is ignored. A single pulse is generated
Bit 0 (IROUTE): Control bit to define the P67 (IROUT) pin function 0 = P67 defined as bi-directional I/O pin 1 = P67 defined as IROUT. Under this condition, the I/O control bit of P67 (Bit 7 of IOC60) must be set to "0"
18 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.2.7 IOCB0 (Pull-Down Control Register)
7
-
6
-
5
/PD55
4
/PD54
3
/PD53
2
/PD52
1
/PD51
0
/PD50
NOTE IOCB0 register is both readable and writable
Bit 7&Bit6:
Not used, fixed to "1". 0 = Enable internal pull-down 1 = Disable internal pull-down
Bit 5 (/PD55): Control bit is used to enable the pull-down of the P55 pin
Bit 4 (/PD54): Control bit is used to enable the pull-down of the P54 pin Bit 3 (/PD53): Control bit is used to enable the pull-down of the P53 pin Bit 2 (/PD52): Control bit is used to enable the pull-down of the P52 pin Bit 1 (/PD51): Control bit is used to enable the pull-down of the P51 pin Bit 0 (/PD50): Control bit is used to enable the pull-down of the P50 pin.
6.2.8 IOCC0 (Open-Drain Control Register)
7
/OD67
6
/OD66
5
-
4
-
3
-
2
-
1
/OD61
0
/OD60
NOTE IOCC0 register is both readable and writable
Bit 7 (/OD67): Control bit is used to enable the open-drain of the P67 pin 0 = Enable open-drain output 1 = Disable open-drain output Bit 6 (/OD66): Control bit is used to enable the open-drain of the P66 pin Bit 5~Bit2: Not used, fixed to "1".
Bit 1 (/OD61): Control bit is used to enable the open-drain of the P61 pin Bit 0 (/OD60): Control bit is used to enable the open-drain of the P60 pin
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 19
EM78P258N
8-Bit Microprocessor with OTP ROM
6.2.9 IOCD0 (Pull-high Control Register)
7
/PH57
6
/PH56
5
/PH55
4
/PH54
3
/PH53
2
/PH52
1
/PH51
0
/PH50
NOTE IOCD0 register is both readable and writable
Bit 7&Bit6:
Not used, fixed to "1". 0 = Enable internal pull-high; 1 = Disable internal pull-high.
Bit 5 (/PH55): Control bit is used to enable the pull-high of the P55 pin.
Bit 4 (/PH54): Control bit is used to enable the pull-high of the P54 pin. Bit 3 (/PH53): Control bit is used to enable the pull-high of the P53 pin. Bit 2 (/PH52): Control bit is used to enable the pull-high of the P52 pin. Bit 1 (/PH51): Control bit is used to enable the pull-high of the P51 pin. Bit 0 (/PH50): Control bit is used to enable the pull-high of the P50 pin.
6.2.10
7
WDTE
IOCE0 (WDT Control & Interrupt Mask Registers 2)
6
EIS
5
ADIE
4
-
3
PSWE
2
PSW2
1
PSW1
0
PSW0
Bit 7 (WDTE): Control bit is used to enable Watchdog Timer 0 = Disable WDT 1 = Enable WDT WDTE is both readable and writable Bit 6 (EIS): Control bit is used to define the function of the P60 (/INT) pin 0 = P60, bi-directional I/O pin 1 = /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC60) must be set to "1"
NOTE When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig. 6-3 (I/O Port and I/O Control Register Circuit for P60(/INT)) under Section 6.4 (I/O Ports). EIS is both readable and writable.
Bit 5 (ADIE): ADIF interrupt enable bit 0 = disable ADIF interrupt 1 = enable ADIF interrupt Bit 4:
20 *
Not used, fixed to "0".
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 3 (PSWE): Prescaler enable bit for WDT 0 = prescaler disable bit, WDT rate is 1:1 1 = prescaler enable bit, WDT rate is set as Bit2 ~ Bit0 Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits PSW2
0 0 0 0 1 1 1 1
PSW1
0 0 1 1 0 0 1 1
PSW0
0 1 0 1 0 1 0 1
WDT Rate
1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
6.2.11
7
LPWTIE
IOCF0 (Interrupt Mask Register)
6
HPWTIE
5
TCCCIE
4
TCCBIE
3
TCCAIE
2
EXIE
1
ICIE
0
TCIE
NOTE IOCF0 register is both readable and writable Individual interrupt is enabled by setting its associated control bit in the IOCF0 and in IOCE0 Bit 5 to "1". Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 6-7 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (LPWTIE): LPWTIF interrupt enable bit 0 = Disable LPWTIF interrupt 1 = Enable LPWTIF interrupt Bit 6 (HPWTIE): HPWTIF interrupt enable bit 0 = Disable HPWTIF interrupt 1 = Enable HPWTIF interrupt Bit 5 (TCCCIE): TCCCIF interrupt enable bit 0 = Disable TCCCIF interrupt 1 = Enable TCCCIF interrupt Bit 4 (TCCBIE): TCCBIF interrupt enable bit 0 = Disable TCCBIF interrupt 1 = Enable TCCBIF interrupt
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 21
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 3 (TCCAIE): TCCAIF interrupt enable bit 0 = Disable TCCAIF interrupt 1 = Enable TCCAIF interrupt Bit 2 (EXIE): EXIF interrupt enable bit 0 = Disable EXIF interrupt 1 = Enable EXIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit 0 = Disable ICIF interrupt 1 = Enable ICIF interrupt Bit 0 (TCIE): TCIF interrupt enable bit. 0 = Disable TCIF interrupt 1 = Enable TCIF interrupt
6.2.12 IOC51 (TCCA Counter)
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on any reset condition and is an UP Counter.
NOTE TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)] TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2(CLK=4)]
6.2.13 IOC61 (TCCB Counter)
An 8-bit clock counter is for the least significant byte of TCCBX (TCCB). It can be read, written, and cleared on any reset condition and is an UP Counter.
6.2.14 IOC71 (TCCBH / MSB Counter)
An 8-bit clock counter is for the most significant byte of TCCBX (TCCBH). It can be read, written, and cleared on any reset condition. When TCCBHE (IOC90) is "0," then TCCBH is disabled. When TCCBHE is"1," then TCCB is a 16-bit length counter.
NOTE When TCCBH is Disabled: TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1(CLK=2)] TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2(CLK=4)] When TCCBH is Enabled: TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1(CLK=2)} TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2(CLK=4)}
22 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.2.15 IOC81 (TCCC Counter)
IOC81 (TCCC) is an 8-bit clock counter that can be extended to 16-bit counter. It can be read, written, and cleared on any reset condition. If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description). Then TCCC value will be TCCC predict value. When HP = 0 or IRE = 0, the TCCC is an UP Counter.
NOTE Under TCCC UP Counter mode: TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1(CLK=2)] TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2(CLK=4)]
When HP = 1 and IRE = 1, TCCC counter scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation.
NOTE Under IR mode: Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC Scale (IOCA0) } FT is system clock: FT = Fosc/1 (CLK=2) FT = Fosc/2 (CLK=4)
6.2.16 IOC91 (Low-Time Register)
The 8-bit Low-time register controls the active or Low segment of the pulse. The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is active. The active period of IR OUT can be calculated as follows:
NOTE Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale(IOCB1) } / FT FT is system clock: FT = Fosc/1 (CLK=2) FT = Fosc/2 (CLK=4)
When an interrupt is generated by the Low time down counter underflow (when enabled), the next instruction will be fetched from address 015H (Low time).
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 23
EM78P258N
8-Bit Microprocessor with OTP ROM
6.2.17
IOCA1 (High Time Register)
The 8-bit High-time register controls the inactive or High period of the pulse. The decimal value of its contents determines the number of oscillator cycles and verifies that the IR OUT pin is inactive. The inactive period of IR OUT can be calculated as follows:
NOTE High time width = {[1+decimal high-time value (IOCA1)] * High time Scale(IOCB1) } / FT FT is system clock: FT=Fosc/1(CLK=2) FT=Fosc/2(CLK=4)
When an interrupt is generated by the High time down counter underflow (when enabled), the next instruction will be fetched from address 012H (High time).
6.2.18
7
HTSE
IOCB1 High/Low Time Scale Control Register)
6
HTS2
5
HTS1
4
HTS0
3
LTSE
2
LTS2
1
LTS1
0
LTS0
Bit 7 (HTSE):
High-time scale enable bit. 0 = scale disable bit, High-time rate is 1:1 1 = scale enable bit, High-time rate is set as Bit 6~Bit 4.
Bit 6 ~ Bit 4 (HTS2 ~ HTS0): High-time scale bits:
HTS2 0 0 0 0 1 1 1 1 HTS1 0 0 1 1 0 0 1 1 HTS0 0 1 0 1 0 1 0 1 High-Time Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (LTSE):
Low-time scale enable bit. 0 = scale disable bit, Low-time rate is 1:1 1 = scale enable bit, Low-time rate is set as Bit 2~Bit 0.
Bit 2 ~ Bit 0 (LTS2 ~ LTS0): Low-time scale bits:
LTS2 0 0 0 0 1 1 1 1 24 * LTS1 0 0 1 1 0 0 1 1 LTS0 0 1 0 1 0 1 0 1 Low-Time Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.2.19 IOCC1 (TCC Prescaler Counter)
TCC prescaler counter can be read and written:
PST2 0 0 0 0 1 1 1 1 PST1 0 0 1 1 0 0 1 1 PST0 0 1 0 1 0 1 0 1 Bit 7 V Bit 6 V V Bit 5 V V V Bit 4 V V V V Bit 3 V V V V V Bit 2 V V V V V V Bit 1 V V V V V V V Bit 0 V V V V V V V V TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
V = valid value
The TCC prescaler counter is assigned to TCC (R1). The contents of the IOCC1 register is cleared when one of the following occurs: a value is written to TCC register a value is written to TCC prescaler bits (Bit3,2,1,0 of CONT) power on reset, /RESET WDT time out reset
6.3
TCC/WDT and Prescaler
There are two 8-bit counters available as prescalers that can be extended to 16-bit counter for the TCC and WDT respectively. The PST2 ~ PST0 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PWR2 ~ PWR0 bits of the IOCE0 register are used to determine the prescaler of WDT. The prescaler counter is cleared by the instructions each time such instructions are written into TCC. The WDT and prescaler will be cleared by the "WDTC" and "SLEP" instructions. Fig. 6-1 (next page) depicts the block diagram of TCC/WDT. TCC (R1) is an 8-bit timer/counter. The TCC clock source can be internal clock or external signal input (edge selectable from the TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). Referring to Fig. 6-1, CLK=Fosc/2 or CLK=Fosc/4 is dependent to the CODE Option bit . CLK=Fosc/2 if the CLKS bit is "0," and CLK=Fosc/4 if the CLKS bit is "1." If TCC signal source is from external clock input, TCC will increase by 1 at every falling edge or rising edge of the TCC pin. TCC pin input time length (kept in High or Low level) must be greater than 1CLK.
NOTE The internal TCC will stop running when sleep mode occurs. However, during AD conversion, when TCC is set to "SLEP" instruction, if the ADWE bit of RE register is enabled, the TCC will keep on running
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 25
EM78P258N
8-Bit Microprocessor with OTP ROM The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during normal mode through software programming. Refer to WDTE bit of IOCE0 register (Section 6.2.10 IOCE0 (WDT Control & Interrupt Mask Registers 2). With no prescaler, the WDT time-out period is approximately 18ms1 or or 4.5ms2.
CLK (Fosc/2 or Fosc/4)
Data Bus
0
8-Bit Counter (IOCC1)
TCC Pin
TE (CONT)
1
MUX
8 to 1 MUX
Prescaler
SYNC 2 cycles
TCC (R1)
TS (CONT)
PSR2~0 (CONT)
TCC overflow interrupt
WDT
8-Bit counter
WDTE (IOCE0)
8 to 1 MUX
Prescaler
WDT Time out
PSW2~0 (IOCE0)
Fig. 6-1 TCC and WDT Block Diagram
6.4
I/O Ports
The I/O registers (Port 5, Port 6, and Port 7) are bi-directional tri-state I/O ports. Port 5 is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain output through software. Port 5 features an input status changed interrupt (or wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port7 are illustrated in Figures 6-2, 6-3, 6-4, & 6-5 (see next page).
1
VDD=5V, WDT Time-out period = 16.5ms 30%. VDD=3V, WDT Time-out period = 18ms 30%. VDD=5V, WDT time-out period = 4.2ms 30%. VDD=3V, WDT time-out period = 4.5ms 30%.
2
26 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
PCRD
Q _ Q
P R C L
D CLK PCWR
PORT
Q _ Q
P R C L
D CLK PDWR
IOD
PDRD 0 1 M U X
NOTE: Open-drain is not shown in the figure.
Fig. 6-2 I/O Port and I/O Control Register Circuit for Port 6 and Port7
PCRD
QPD R _ CLK QC L
PCWR
PORT Bit 6 of IOCE DPQ R CLK _ CQ L
QPD R _ CLK QC L 0 1
IOD PDWR
M U X PDRD
INT
NOTE: Open-drain is not shown in the figure.
Fig. 6-3 I/O Port and I/O Control Register Circuit for P60(/INT) Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 27
EM78P258N
8-Bit Microprocessor with OTP ROM
PCRD
Q Q
D
CLK
PCWR
P50 ~ P57
PORT Q Q D
CLK
IOD PDWR
0 1
M U X
PDRD TI n
D
CLK
Q
Q
NOTE: Pull-high (down) is not shown in the figure.
Fig. 6-4 I/O Port and I/O Control Register Circuit for Port 50 ~ P57
I O C F.1
R F.1
TI 0 TI 1
TI 8
....
Fig. 6-5 Port 5 Block Diagram with Input Change Interrupt/Wake-up
28 * Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.4.1 Usage of Port 5 Input Change Wake-up/Interrupt Function
(1) Wake-up (a) Before SLEEP 1. Disable WDT 2. Read I/O Port 5 (MOV R5,R5) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Execute "SLEP" instruction (b) After wake-up Next instruction (2) Wake-up and Interrupt (a) Before SLEEP 1. Disable WDT 2. Read I/O Port 5 (MOV R5,R5) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Enable interrupt (Set IOCF0 ICIE =1) 6. Execute "SLEP" instruction (b) After wake-up 1. IF "ENI" Interrupt vector (006H) 2. IF "DISI" Next instruction
(3) Interrupt (a) Before Port 5 pin change 1. Read I/O Port 5 (MOV R5,R5) 2. Execute "ENI" or "DISI" 3. Enable interrupt (Set IOCF0 ICIE =1) (b) After Port 5 pin changed (interrupt) 1. IF "ENI" Interrupt vector (006H) 2. IF "DISI" Next instruction
6.5
RESET and Wake-up
6.5.1 RESET and Wake-up Operation
A RESET is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled). The device is kept under RESET condition for a period of approximately 18ms3 (except in LXT mode ) after the reset is detected. When in LXT mode, the reset time is 500ms. Two choices (18ms3 or 4.5ms4) are available for WDT-time out period. Once RESET occurs, the following functions are performed (the initial address is 000h): The oscillator continues running, or will be started (if under sleep mode) The Program Counter (R2) is set to all "0" All I/O port pins are configured as input mode (high-impedance state) The Watchdog Timer and prescaler are cleared When power is switched on, the upper 3 bits of R3 is cleared The CONT register bits are set to all "1" except for the Bit 6 (INT flag) The IOCB0 register bits are set to all "1"
3
VDD=5V, WDT Time-out period = 16.5ms 30%. VDD=3V, WDT Time-out period = 18ms 30%.
VDD=5V, WDT Time-out period = 4.2ms 30%. VDD=3V, WDT Time-out period = 4.5ms 30%. Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
4
* 29
EM78P258N
8-Bit Microprocessor with OTP ROM The IOCC0 register bits are set to all "1" The IOCD0 register bits are set to all "1" Bits 7, 5, and 4 of IOCE0 register is cleared Bit 5 and 4 of RC register is cleared RF and IOCF0 registers are cleared Executing the "SLEP" instruction will assert the sleep (power down) mode. While entering into sleep mode, the Oscillator, TCC, TCCA, TCCB, and TCCC are stopped. The WDT (if enabled) is cleared but keeps on running. During AD conversion, when "SLEP" instruction I set; the Oscillator, TCC, TCCA, TCCB, and TCCC keep on running. The WDT (if enabled) is cleared but keeps on running. The controller can be awakened byCase 1 Case 2 Case 3 Case 4 External reset input on /RESET pin WDT time-out (if enabled) Port 5 input status changes (if ICWE is enabled) AD conversion completed (if ADWE enable).
The first two cases (1 & 2) will cause the EM78P258N to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Cases 3, &4 are considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from address 0x06 (Case 3), and 0x0C (Case 4) after wake-up. If DISI is executed before SLEP, the execution will restart from the instruction next to SLEP after wake-up. Only one of Cases 1 to 4 can be enabled before entering into sleep mode. That is: Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the EM78P258N can be awaken only with Case 1 or Case 2. Refer to the section on Interrupt (Section 6.6 below) for further details. Case [b] If Port 5 Input Status Change is used to wake-up EM78P258N and the ICWE bit of RE register is enabled before SLEP. At the same time, the WDT must be disabled. Hence, the EM78P258N can be awaken only with Case 3. Wake-up time is dependent on oscillator mode. Under RC mode the reset time is 32 clocks. In High XTAL mode, reset time is 2ms and 32clocks; and in low XTAL mode, the reset time is 500ms.
30 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM Case [d] If AD conversion is completed, it wakes-up EM78P258N and ADWE bit of RE register is enabled before SLEP. At the same time, WDT must be disabled by software. Hence, the EM78P258N can be awaken only with Case 4. The wake-up time is 15 TAD (ADC clock period). If Port 5 Input Status Change Interrupt is used to wake up the EM78P258N (as in Case [b] above), the following instructions must be executed before SLEP: BC R3, 7 MOV A, @00xx1110b IOW IOCE0 WDTC MOV R5, R5 ENI (or DISI) MOV A, @xxxxxx1xb MOV RE MOV A, @xxxxxx1xb IOW IOCF0 SLEP ; Select Segment 0 ; Select WDT prescaler and Disable WDT ; ; ; ; Clear WDT and prescaler Read Port 5 Enable (or disable) global interrupt Enable Port 5 input change wake-up bit
; Enable Port 5 input change interrupt ; Sleep
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 31
EM78P258N
8-Bit Microprocessor with OTP ROM 6.5.1.1 Wake-Up and Interrupt Modes Operation Summary All categories under Wake-up and Interrupt modes are summarized below.
Signal Sleep Mode Normal Mode
DISI + IOCF0 (EXIE) bit2=1 INT Pin N/A Next Instruction + Set RF (EXIF)=1 ENI + IOCF0 (EXIE) bit2=1 Interrupt Vector (003H) + Set RF (EXIF)=1 RE (ICWE) bit1=0, IOCF0 (ICIE) bit1=0 Oscillator, TCC, TCCX and IR/PWM are stopped. Port5 input status changed wake-up is invalid. RE (ICWE) bit1=0, IOCF0 (ICIE) bit1=1 Set RF (ICIF)=1, Oscillator, TCC, TCCX and IR/PWM are stopped. Port5 input status changed wake-up is invalid. Port5 Input Status Change RE (ICWE) bit1=1, IOCF0 (ICIE) bit1=0 Wake-up + Next Instruction Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ICWE) bit1=1, DISI + IOCF0 (ICIE) bit1=1 Wake-up + Next Instruction + Set RF (ICIF)=1 Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ICWE) bit1=1, ENI + IOCF0 (ICIE) bit1=1 Wake-up + Interrupt Vector (006H) + Set RF (ICIF)=1 Oscillator, TCC, TCCX and IR/PWM are stopped. N/A N/A DISI + IOCF0 (ICIE) bit1=1 Next Instruction + Set RF (ICIF)=1 ENI + IOCF0 (ICIE) bit1=1 Interrupt Vector(006H)+ Set RF (ICIF)=1 DISI + IOCF0 (TCIE) bit0=1 TCC Over Flow N/A Next Instruction + Set RF (TCIF)=1 ENI + IOCF0 (TCIE) bit0=1 Interrupt Vector (009H) + Set RF (TCIF)=1 RE (ADWE) bit3=0, IOCE0 (ADIE) bit5=0 Clear R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ADWE) bit3=0, IOCE0 (ADIE) bit5=1 Set RF (ADIF)=1, R9 (ADRUN)=0, ADC is stopped, AD conversion wake-up is invalid. Oscillator, TCC, TCCX and IR/PWM are stopped. RE (ADWE) bit3=1, IOCE0 (ADIE) bit5=0 AD Conversion Wake-up + Next Instruction, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed. RE (ADWE) bit3=1, DISI + IOCE0 (ADIE) bit5=1 Wake-up + Next Instruction + RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed. RE (ADWE) bit3=1, ENI + IOCE0 (ADIE) bit5=1 Wake-up + Interrupt Vector (00CH)+ RE (ADIF)=1, Oscillator, TCC, TCCX and IR/PWM keep on running. Wake-up when ADC completed. Interrupt Vector (00CH) + Set RE (ADIF)=1 ENI + IOCE0 (ADIE) bit5=1 Next Instruction + RE (ADIF)=1 DISI + IOCE0 (ADIE) bit5=1 N/A N/A N/A N/A AD conversion interrupted is invalid IOCE0 (ADIE) bit5=0 N/A IOCF0 (ICIE) bit1=0 Port5 input status change interrupted is invalid N/A
32 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
Signal
IR/PWM underflow interrupt
Sleep Mode
Normal Mode
DISI + IOCF0 (HPWTIF) bit6=1 Next Instruction + Set RF (HPWTIE)=1 ENI + IOCF0 (HPWTIF) bit6 =1 Interrupt Vector (012H) + Set RF (HPWTIE)=1 DISI + IOCF0 (LPWTIF) bit7=1
N/A (High-pulse width imer underflow interrupt) IR/PWM underflow interrupt N/A (Low-pulse width timer underflow interrupt)
Next Instruction + Set RF (LPWTIE)=1 ENI + IOCF0 (LPWTIF) bit7 =1 Interrupt Vector (015H) + Set RF (LPWTIE)=1 DISI + IOCF0 (TCCAIE) bit3=1
TCCA Over Flow
N/A
Next Instruction + Set RF (TCCAIF)=1 ENI + IOCF0 (TCCAIE) bit3=1 Interrupt Vector (018H) + Set RF (TCCAIF)=1 DISI + IOCF0 (TCCBIE) bit4=1
TCCB Over Flow
N/A
Next Instruction + Set RF (TCCBIF)=1 ENI + IOCF0 (TCCBIE) bit4=1 Interrupt Vector (01BH) + Set RF (TCCBIF)=1 DISI + IOCF0 (TCCCIE) bit5=1
TCCC Over Flow
N/A
Next Instruction + Set RF (TCCCIF)=1 ENI + IOCF0 (TCCCIE) bit5=1 Interrupt Vector (01EH) + Set RF (TCCCIF)=1
WDT Time Out IOCE (WDTE) bit7=1
Wake-up + Reset (address 0x00)
Reset (address 0x00)
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 33
EM78P258N
8-Bit Microprocessor with OTP ROM 6.5.1.2 Register Initial Values after Reset The following summarizes the initialized values for registers.
Address Name Reset Type
Bit Name Type N/A IOC50 Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On N/A IOC60 /RESET and WDT Wake-Up from Pin Change Bit Name Power-On N/A IOC70 /RESET and WDT Wake-Up from Pin Change Bit Name N/A IOC80 Power-On /RESET and WDT Wake-Up from Pin Change Bit Name N/A IOC90 Power-On /RESET and WDT Wake-Up from Pin Change Bit Name N/A IOCA0 (IR CR) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name N/A IOCB0 (PDCR) Power-On /RESET and WDT Wake-Up from Pin Change Bit Name N/A IOCC0 (ODCR) Power-On /RESET and WDT Wake-Up from Pin Change
Bit 7
C57 A 0 0 0 B 1 1 P
Bit 6
C56 A 0 0 0 B 1 1 P
Bit 5
C55 - 1 1 P - 1 1 P X 0 0 P - 0 0 P - 0 0 P
Bit 4
C54 - 1 1 P - 1 1 P X 0 0 P - 0 0 P - 0 0 P
Bit 3
C53 - 1 1 P - 1 1 P X 0 0 P - 0 0 P X 0 0 P IRE 0 0 P /PD53 1 1 P - 1 1 P
Bit 2
C52 - 1 1 P - 1 1 P X 0 0 P
Bit 1
C51 - 1 1 P C61 1 1 P X 0 0 P
Bit 0
C50 - 1 1 P C60 1 1 P C70 1 1 P
C67 1 1 P X 0 0 P X 0 0 P
C66 1 1 P X 0 0 P X 0 0 P
TCCAEN TCCATS TCCATE 0 0 P TCCCEN 0 0 P HF 0 0 P /PD52 1 1 P - 1 1 P 0 0 P - 0 0 P LGP 0 0 P /PD51 1 1 P /OD61 1 1 P 0 0 P - 0 0 P IROUTE 0 0 P /PD50 1 1 P /OD60 1 1 P
TCCBHE TCCBEN 0 0 P 0 0 P
TCCCSE TCCCS2 TCCCS1 TCCCS0 0 0 P - 1 1 P /OD67 1 1 P 0 0 P - 1 1 P /OD66 1 1 P 0 0 P /PD55 1 1 P - 1 1 P 0 0 P /PD54 1 1 P - 1 1 P
34 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On
Bit 7
- 1 1 P WDTC 0 0 P
Bit 6
- 1 1 P EIS 0 0 P
Bit 5
/PH55 1 1 P ADIE 0 0 P
Bit 4
/PH54 1 1 P - 0 0 P
Bit 3
/PH53 1 1 P PSWE 0 0 P
Bit 2
/PH52 1 1 P PSW2 0 0 P EXIE 0 0 P TCCA2 0 0 P TCCB2 0 0 P
Bit 1
/PH51 1 1 P PSW1 0 0 P ICIE 0 0 P TCCA1 0 0 P TCCB1 0 0 P
Bit 0
/PH50 1 1 P PSW0 0 0 P TCIE 0 0 P TCCA0 0 0 P TCCB0 0 0 P
N/A
IOCD0 (PHCR)
N/A
IOCE0
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
LPWTIE HPWTIE TCCCIE TCCBIE TCCAIE 0 0 P TCCA7 0 0 P TCCB7 0 0 P 0 0 P TCCA6 0 0 P TCCB6 0 0 P 0 0 P TCCA5 0 0 P TCCB5 0 0 P 0 0 P TCCA4 0 0 P TCCB4 0 0 P 0 0 P TCCA3 0 0 P TCCB3 0 0 P
N/A
IOCF0
/RESET and WDT Wake-Up from Pin Change Bit Name
N/A
IOC51 (TCCA)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
N/A
IOC61 (TCCB)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
TCCBH7 TCCBH6 TCCBH5 TCCBH4 TCCBH3 TCCBH2 TCCBH1 TCCBH0 0 0 P TCCC7 0 0 P LTR7 0 0 P 0 0 P TCCC6 0 0 P LTR6 0 0 P 0 0 P TCCC5 0 0 P LTR5 0 0 P 0 0 P TCCC4 0 0 P LTR4 0 0 P 0 0 P TCCC3 0 0 P LTR3 0 0 P 0 0 P TCCC2 0 0 P LTR2 0 0 P 0 0 P TCCC1 0 0 P LTR1 0 0 P 0 0 P TCCC0 0 0 P LTR0 0 0 P
N/A
IOC71 (TCCBH)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
N/A
IOC81 (TCCC)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
N/A
IOC91 (LTR)
Power-On /RESET and WDT Wake-Up from Pin Change
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 35
EM78P258N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
Bit 7
HTR7 0 0 P HTSE 0 0 P
Bit 6
HTR6 0 0 P HTS2 0 0 P
Bit 5
HTR5 0 0 P HTS1 0 0 P
Bit 4
HTR4 0 0 P HTS0 0 0 P
Bit 3
HTR3 0 0 P LTSE 0 0 P
Bit 2
HTR2 0 0 P LTS2 0 0 P
Bit 1
HTR1 0 0 P LTS1 0 0 P
Bit 0
HTR0 0 0 P LTS0 0 0 P
N/A
IOCA1 (HTR)
N/A
IOCB1 (HLTS)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
TCCPC7 TCCPC6 TCCPC5 TCCPC4 TCCPC3 TCCPC2 TCCPC1 TCCPC0 0 0 P INTE 1 1 P - U P P - 0 0 P - 0 0 0 0 P INT 0 0 P - U P P - 0 0 P - 0 0 0 0 P TS 1 1 P - U P P - 0 0 P - 0 0 0 0 P TE 1 1 P - U P P - 0 0 P - 0 0 0 0 P PSTE 0 0 P - U P P - 0 0 P - 0 0 0 0 P PST2 0 0 P - U P P - 0 0 P - 0 0 0 0 P PST1 0 0 P - U P P - 0 00 P - 0 0 0 0 P PST0 0 0 P - U P P - 0 0 P - 0 0
N/A
IOCC1 (TCCPC)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On
N/A
CONT
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x00
R0(IAR)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x01
R1(TCC)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x02
R2(PC)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
Jump to address 0x06 or continue to execute next instruction RST 0 0 P IOCS 0 0 P PS0 0 0 P T 1 T T P 1 t t Z U P P DC U P P C U P P
0x03
R3(SR)
/RESET and WDT Wake-Up from Pin Change
36 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-On
Bit 7
X 0 0 0 P57 1 1 P P67 1 1 P - 0 0 P - 0 0 0 VREFS 0 0 P CALI 0 0 P AD11 U U P
Bit 6
BS 0 0 P P56 1 1 P P66 1 1 P - 0 0 P - 0 0 0 CKR1 0 0 P SIGN 0 0 P AD10 U U P
Bit 5
X U P P P55 1 1 P P65 1 1 P - 0 0 P - 0 0 0 CKR0 0 0 P VOF[2] 0 0 P AD9 U U P
Bit 4
X U P P P54 1 1 P P64 1 1 P - 0 0 P - 0 0 0 ADRUN 0 0 P VOF[1] 0 0 P AD8 U U P
Bit 3
X U P P P53 1 1 P P63 1 1 P - 0 0 P ADE3 0 0 P ADPD 0 0 P VOF[0] 0 0 P AD7 U U P
Bit 2
X U P P P52 1 1 P P62 1 1 P - 0 0 P ADE2 0 0 P - 0 0 0 - 0 0 P AD6 U U P
Bit 1
X U P P P51 1 1 P P61 1 1 P - 0 0 P ADE1 0 0 P ADIS1 0 0 P - 0 0 P AD5 U U P
Bit 0
X U P P P50 1 1 P P60 1 1 P P70 1 1 P ADE0 0 0 P ADIS0 0 0 P - 0 0 P AD4 U U P
0x04
R4(RSR)
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x05
R5
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x06
R6
/RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x7
R7
/RESET and WDT Wake-Up from Pin Change Bit Name
0x8
R8 (AISR)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0x9
R9 (ADCON)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0xA
RA (ADOC)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
0XB
(ADDATA) /RESET and WDT Wake-Up from Pin Change
RB
Power-On
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 37
EM78P258N
8-Bit Microprocessor with OTP ROM
Address
Name
Reset Type
Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
Bit 7
"0" 0 0 0 AD7 U U P -0 0 P
Bit 6
"0" 0 0 0 AD6 U U P - 0 0 P
Bit 5
"0" 0 0 0 AD5 U U P ADIF 0 0 P
Bit 4
"0" 0 0 0 AD4 U U P - 0 0 P
Bit 3
AD11 U U P AD3 U U P ADWE 0 0 P
Bit 2
AD10 U U P AD2 U U P - 0 0 P EXIF 0 0 P - U P P
Bit 1
AD9 U U P AD1 U U P ICWE 0 0 P ICIF 0 0 P - U P P
Bit 0
AD8 U U P AD0 U U P - 0 0 P TCIF 0 0 P - U P P
0XC
RC (ADDATA1H)
0XD
(ADDATA1L0) /RESET and WDT Wake-Up from Pin Change Bit Name
RD
Power-On
0xE
RE (ISR2)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name
LPWTIF HPWTIF TCCCIF TCCBIF TCCAIF 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P 0 0 P - U P P
0xF
RF (ISR1)
Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On
0x10~0x3F
R10~R3F
/RESET and WDT Wake-Up from Pin Change
Legend: X: not used P: previous value before reset
U: unknown or don't care. t: check table under Section 6.5.2
6.5.1.3 Controller Reset Block Diagram
VDD
D Oscillator
CLK CLR
Power-On Reset Voltage Detector
Q
CLK
ENWDTB
WDT Timeout
WDT /RESET
Setup time
Reset
Fig. 6-6 Controller Reset Block Diagram 38 * Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.5.2 The T and P Status under STATUS (R3) Register
A RESET condition is initiated by one of the following events: 1. Power-on reset 2. /RESET pin input "low" 3. WDT time-out (if enabled). The values of RST, T, and P as listed in the table below, are used to check how the processor wakes up. Reset Type
Power-on /RESET during Operating mode /RESET wake-up during SLEEP mode WDT during Operating mode WDT wake-up during SLEEP mode Wake-up on pin change during SLEEP mode
RST
0 0 0 0 0 1
T
1 *P 1 0 0 1
P
1 *P 0 1 0 0
*P: Previous status before reset
The following shows the events that may affect the status of T and P. Event
Power-on WDTC instruction WDT time-out SLEP instruction Wake-up on pin changed during SLEEP mode
RST
0 *P 0 *P 1
T
1 1 0 1 1
P
1 1 *P 0 0
*P: Previous value before reset
6.6
Interrupt
The EM78P258N has five interrupts as listed below: 1. TCC, TCCA, TCCB, TCCC overflow interrupt 2. Port 5 Input Status Change Interrupt 3. External interrupt [(P60, /INT) pin] 4. Analog to Digital conversion completed 5. IR/PWM underflow interrupt Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV R5,R5") is necessary. Each Port 5 pin will have this feature if its status changes. The Port 5 Input Status Change Interrupt will wake-up the EM78P258N from the sleep mode if it is enabled prior to going into the sleep mode by executing SLEP instruction. When wake-up occurs, the controller will continue to execute program in-line if the global interrupt is disabled. If enabled, the global interrupt will branch out to the interrupt vector 006H.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 39
EM78P258N
8-Bit Microprocessor with OTP ROM External interrupt equipped with digital noise rejection circuit (input pulse less than 8 system clocks time) is eliminated as noise. However, under Low XTAL oscillator (LXT) mode the noise rejection circuit will be disabled. Edge selection is possible with INTE of CONT. When an interrupt is generated by the External interrupt (when enabled), the next instruction will be fetched from address 003H. Refer to the Word 1 Bits 9 & 8 (Section 6.14.2, Code Option Register (Word1)) for digital noise rejection definition RF and RE are the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF0 and IOCE0 are interrupt mask registers. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. The flag (except for the ICIF bit) in the Interrupt Status Register (RF) is set regardless of the ENI execution. Note that the result of RF will be the logic AND of RF and IOCF0 (refer to figure below). The RETI instruction ends the interrupt routine and enables the global interrupt (the ENI execution). When an interrupt is generated by the Timer clock/counter (if enabled), the next instruction will be fetched from Address 009, 018, 01B, and 01EH (TCC, TCCA, TCCB, and TCCC respectively). When an interrupt is generated by the AD conversion is completed (if enabled), the next instruction will be fetched from Address 00CH. When an interrupt is generated by the High time / Low time down counter underflow (when enabled), the next instruction will be fetched from Address 012 and 015H (High time and Low time respectively). Before the interrupt subroutine is executed, the contents of ACC and the R3 and R4 registers will be saved by the hardware. If another interrupt occurs, the ACC, R3, and R4 will be replaced by the new interrupt. After the interrupt service routine is completed, the ACC, R3, and R4 registers are restored.
40 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
VCC
D /IRQn
P R CLK C L RF
Q _ Q RFRD
IRQn INT IRQm ENI/DISI
Q _ Q
P R C L
D CLK IOCFWR
IOD
IOCF /RESET
IOCFRD
RFWR
Fig. 6.7 Interrupt Input Circuit
Interrupt sources ACC ENI/DISI R3 R4
Interrupt occurs RETI
STACKACC STACKR3 STACKR4
Fig. 6.8 Interrupt Backup Diagram
In EM78P258N, each individual interrupt source has its own interrupt vector as depicted in the table below. Interrupt Vector
003H 006H 009H 00CH 012H 015H 018H 01BH 01EH
Interrupt Status
External interrupt Port 5 pin change TCC overflow interrupt AD conversion complete interrupt High-pulse width timer underflow interrupt Low-pulse width timer underflow interrupt TCCA overflow interrupt TCCB overflow interrupt TCCC overflow interrupt
Priority*
1 2 3 4 5 6 7 8 9
*Priority: 1 = highest ; 9 = lowest priority
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 41
EM78P258N
8-Bit Microprocessor with OTP ROM
6.7
Analog-To-Digital Converter (ADC)
The analog-to-digital circuitry consisted of a 4-bit analog multiplexer; three control registers (AISR/R8, ADCON/R9, & ADOC/RA), three data registers (ADDATA/RB, ADDATA1H/RC, & ADDATA1L/RD), and an ADC with 12-bit resolution as shown in the functional block diagram below. The analog reference voltage (Vref) and the analog ground are connected via separate input pins. The ADC module utilizes successive approximation to convert the unknown analog signal into a digital value. The result is fed to the ADDATA, ADDATA1H, and ADDATA1L. Input channels are selected by the analog input multiplexer via the ADCON register Bits ADIS1 and ADIS0.
Vref
ADC3 ADC2 ADC1 ADC0 Fsco
4-1 MUX
ADC ( successive approximation )
Power-Down
Start to Convert
Internal RC
7~0
AISR
1 ADCON 0
6 ADCON
5 RF
3
11 10
9
8
7
6
5
4
3
2
1
0
4
ADCON
3
ADDATA1H
ADDATA1L
DATA BUS
Fig. 6-9 Analog-to-Digital Conversion Functional Block Diagram
6.7.1 ADC Control Register (AISR/R8, ADCON/R9, ADOC/RA)
6.7.1.1 R8 (AISR: ADC Input Select Register) 7
-
6
-
5
-
4
-
3
ADE3
2
ADE2
1
ADE1
0
ADE0
AISR register defines the Port 5 pins as analog inputs or as digital I/O, individually. Bit 7 ~ 4: Not used
Bit 3 (ADE3 ): AD converter enable bit of P53 pin 0 = Disable ADC3, P53 acts as I/O pin 1 = Enable ADC3 acts as analog input pin Bit 2 (ADE2 ): AD converter enable bit of P52 pin 0 = Disable ADC2, P53 acts as I/O pin 1 = Enable ADC2 acts as analog input pin
42 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 1 (ADE1 ): AD converter enable bit of P51 pin 0 = Disable ADC1, P51 acts as I/O pin 1 = Enable ADC1 acts as analog input pin Bit 0 (ADE0 ): AD converter enable bit of P50 pin 0 = Disable ADC0, P50 acts as I/O pin 1 = Enable ADC0 acts as analog input pin 6.7.1.2 R9 (ADCON: AD Control Register) 7
VREFS
6
CKR1
5
CKR0
4
ADRUN
3
ADPD
2
-
1
ADIS1
0
ADIS0
ADCON register controls the operation of the AD conversion and decides which pin should be currently active. Bit 7(VREFS): The input source of the Vref of the ADC 0 = The Vref of the ADC is connected to Vdd (default value), and the P54/VREF pin carries out the P54 function 1 = The Vref of the ADC is connected to P54/VREF
NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. IF P54/TCC/VREF acts as VREF analog input pin, then CONT Bit 5 (TS) must be "0".. The P54/TCC/VREF pin priority is as follows: P54/TCC/VREF Pin Priority High VREF Medium TCC Low P54
Bit 6 ~ Bit 5 (CKR1 ~ CKR0): The ADC prescaler oscillator clock rate 00 = 1: 4 (default value) 01 = 1: 16 10 = 1: 64 11 = 1: WDT ring oscillator frequency
CKR0:CKR1 Operation Mode Max. Operation Frequency 00 01 10 11 Fsco/4 Fsco/16 Fsco/64 Internal RC 1 MHz 4 MHz 16MHz 1 MHz
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 43
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 4 (ADRUN): ADC starts to RUN. 1 = an AD conversion is started. This bit can be set by software. 0 = reset on completion of the conversion. This bit cannot be reset though software. Bit 3 (ADPD): ADC Power-down mode. 1 = ADC is operating 0 = switch off the resistor reference to save power even while the CPU is operating. Bit 2: Not used
Bit 1 ~ Bit 0 (ADIS1 ~ ADIS0): Analog Input Select 00 = ADIN0/P50 01 = ADIN1/P51 10 = ADIN2/P52 11 = ADIN3/P53 These bits can only be changed when the ADIF bit and the ADRUN bit are both LOW. 6.7.1.3 RA (ADOC: AD Offset Calibration Register) 7
CALI
6
SIGN
5
VOF[2]
4
VOF[1]
3
VOF[0]
2
-
1
-
0
-
Bit 7 (CALI): Calibration enable bit for ADC offset 0 = Calibration disable 1 = Calibration enable Bit 6 (SIGN): Polarity bit of offset voltage 0 = Negative voltage 1 = Positive voltage Bit 5 ~ Bit 3 (VOF[2] ~ VOF[0]): Offset voltage bits. VOF[2] VOF[1] VOF[0] EM78P258N
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0LSB 2LSB 4LSB 6LSB 8LSB 10LSB 12LSB 14LSB
ICE259N
0LSB 1LSB 2LSB 3LSB 4LSB 5LSB 6LSB 7LSB
Bit 2 ~ Bit 0: Unimplemented, read as `0'.
44 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.7.2 ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD)
When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.
6.7.3 ADC Sampling Time
The accuracy, linearity, and speed of the successive approximation of AD converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2s for each K of the analog source impedance and at least 2s for the low-impedance source. The maximum recommended impedance for analog source is 10K at Vdd=5V. After the analog input channel is selected, this acquisition time must be done before the conversion is started.
6.7.4 AD Conversion Time
CKR0 and CKR1 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at the maximum frequency without sacrificing the AD conversion accuracy. For the EM78P258N, the conversion time per bit is about 4s. The table below shows the relationship between Tct and the maximum operating frequencies.
CKR0:CKR1 Operation Mode 00 01 10 11 Fsco/4 Fsco/16 Fsco/64 Internal RC Max. Operation Frequency 1 MHz 4MHz 16MHz - Max. Conversion Rate/Bit 250kHz (4us) 250kHz (4us) 250kHz( 4us) 14Kkz (71us) Max. Conversion Rate 15*4us=60us(16.7kHz) 15*4us=60us(16.7kHz) 15*4us=60us(16.7kHz) 15*71us=1065us(0.938kHz)
NOTE
Pin not used as an analog input pin can be used as regular input or output pin. During conversion, do not perform output instruction to maintain precision for all of the pins.
6.7.5 ADC Operation during Sleep Mode
In order to obtain a more accurate ADC value and reduce power consumption, the AD conversion remains operational during sleep mode. As the SLEP instruction is executed, all the MCU operations will stop except for the Oscillator, TCC, TCCA, TCCB, TCCC and AD conversion. The AD Conversion is considered completed as determined by: 1. ADRUN bit of R9 register is cleared ("0" value) 2. ADIF bit of RE register is set to "1"
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 45
EM78P258N
8-Bit Microprocessor with OTP ROM 3. ADWE bit of RE register is set to "1." Wake-up from ADC conversion (where it remains in operation during sleep mode) 4. Wake-up and executes the next instruction if ADIE bit of IOCE0 is enabled and the "DISI" instruction is executed 5. Wake-up and enters into Interrupt vector (address 0x00C) if ADIE bit of IOCE0 is enabled and the "ENI" instruction is executed 6. Enters into Interrupt vector (address 0x00C) if ADIE bit of IOCE0 is enabled and the "ENI" instruction is executed. The results are fed into the ADDATA, ADDATA1H, and ADDATA1L registers when the conversion is completed. If the ADIE is enabled, the device will wake up. Otherwise, the AD conversion will be shut off, no matter what the status of ADPD bit is.
6.7.6 Programming Process/Considerations
6.7.6.1 Programming Process Follow these steps to obtain data from the ADC: 1. Write to the four bits (ADE3:ADE0) on the R8 (AISR) register to define the characteristics of R5 (digital I/O, analog channels, or voltage reference pin) 2. Write to the R9/ADCON register to configure AD module: a) Select ADC input channel (ADIS1:ADIS0) b) Define AD conversion clock rate (CKR1:CKR0) c) Select the VREFS input source of the ADC d) Set the ADPD bit to 1 to begin sampling 3. Set the ADWE bit, if the wake-up function is employed 4. Set the ADIE bit, if the interrupt function is employed 5. Write "ENI" instruction, if the interrupt function is employed 6. Set the ADRUN bit to 1 7. Write "SLEP" instruction or Polling. 8. Wait for wake-up, ADRUN bit is cleared ("0" value), interrupt flag (ADIF) to be set "1," or the ADC interrupt to occurs 9. Read the ADDATA or ADDATA1H and ADDATA1L conversion data registers. If ADC input channel changes at this time, the ADDATA, ADDATA1H, and ADDATA1L values can be cleared to `0' 10. Clear the interrupt flag bit (ADIF) 11. For next conversion, go to Step 1 or Step 2 as required. At least 2 Tct is required before the next acquisition starts.
46 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
NOTE In order to obtain accurate values, it is necessary to avoid any data transition on I/O pins during AD conversion. 6.7.6.2 Sample Demo Programs A. Define a General Registers R_0 == 0 PSW == 3 PORT5 == 5 PORT6 == 6 R_E== 0XE ; Indirect addressing register ; Status register
; Interrupt status register
B. Define a Control Register IOC50 == 0X5 IOC60 == 0X6 C_INT== 0XF ; Control Register of Port 5 ; Control Register of Port 6 ; Interrupt Control Register
C. ADC Control Register ADDATA == 0xB AISR == 0x08 ADCON == 0x9 ; The contents are the results of ADC ; ADC input select register ;7 6 5 4 3 2 1 0 ; VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0
D. Define Bits in ADCON ADRUN == 0x4 ADPD == 0x3 E. Program Starts ORG 0 JMP INITIAL ; Initial address ; ; ADC is executed as the bit is set ; Power Mode of ADC
ORG 0x0C ; Interrupt vector JMP CLRRE ; ; ;(User program section) ; ; CLRRE: MOV A,RE AND A, @0BXX0XXXXX ; To clear the ADIF bit, "X" by application MOV RE,A BS ADCON, ADRUN ; To start to execute the next AD conversion if necessary
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 47
EM78P258N
8-Bit Microprocessor with OTP ROM RETI INITIAL: MOV A,@0B00000001 MOV AISR,A MOV A,@0B00001000 MOV ADCON,A
; To define P50 as an analog input ; To select P50 as an analog input channel, and AD power on ; To define P50 as an input pin and set clock rate at fosc/16
En_ADC: MOV A, @0BXXXXXXX1 ; To define P50 as an input pin, and the others IOW PORT5 ; are dependent on applications MOV A, @0BXXXX1XXX ; Enable the ADWE wake-up function of ADC, "X" by application MOV RE,A MOV A, @0BXXXX1XXX ; Enable the ADIE interrupt function of ADC, "X" by application IOW C_INT ENI ; Enable the interrupt function BS ADCON, ADRUN ; Start to run the ADC
; If the interrupt function is employed, the following three lines may be ignored ;If Sleep: SLEP ; ;(User program section) ; or ;If Polling: POLLING: JBC ADCON, ADRUN JMP POLLING
; To check the ADRUN bit continuously; ; ADRUN bit will be reset as the AD conversion is completed
; ;(User program section) ;
48 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.8
Infrared Remote Control Application/PWM Waveform Generation
6.8.1 Overview
This LSI can easily output infrared carrier or PWM standard waveform. As illustrated below, the IR and PWM waveform generation function include an 8-bit down count timer/counter, high-time, low-time, and IR control register. The IROUT pin waveform is determined by IOCA0 (IR and TCCC scale control register), IOCB1 (high-time rate, low-time rate control register), IOC81 (TCCC counter), IOCA1 (high-time register), and IOC91 (low-time register).
FT:CLK(Fosc)
8 Bit counter 8 Bit counter Scale (IOCA0) Scale (IOCB1) 8-to-1 MUX 8
8 Bit counter Scale (IOCB1)
8-to-1 MUX
8-to-1 MUX
Auto-reload buffer (High-time)(IOCA1)
8bit binary down counter 8
8bit binary down counter 8
8
Auto-reload buffer (Low-time)(IOC91)
Fcarrier
8bit binary down counter 8 Auto-reload buffer (TCCC)(IOC81)
H/W Modulator
HF
LG
IR
IROUT
Underflow Interrupt HPWTIF LPWTIF
Fig. 6-10 IR/PWM System Block Diagram
NOTE Details of the Fcarrier high time width and low time width are explained below: Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC Scale(IOCA0) }
High time width = { [1+decimal high-time value (IOCA1)] * High time Scale(IOCB1) } / FT Low time width = { [1+decimal low-time value (IOC91)] * Low time Scale(IOCB1) } / FT Where FT is the system clock FT=Fosc/1(CLK=2) FT=Fosc/2(CLK=4)
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 49
EM78P258N
8-Bit Microprocessor with OTP ROM When an interrupt is generated by the High time down counter underflow (when enabled), the next instruction will be fetched from address 018 and 01BH (High time and Low time respectively).
6.8.2 Function Description
The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low-time segments of the pulse.
Fcarrier
low time width high time width
low time width
high time width
HF IRE IROUT
start
Fig. 6-11a LGP=0, HF=1, IROUT Pin Output Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is determined by the high time width and low time width instead. This mode can produce standard PWM waveform
Fcarrier
low time width
high time width
low time width
high time width
HF
start
IRE IROUT
Fig. 6-11b LGP=0, HF=0, IROUT Pin Output Waveform
50 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM The following figure shows LGP=0 and HF=1. The IROUT waveform modulates the Fcarrier waveform at low-time segments of the pulse. When IRE goes low from high, the output waveform of IROUT will keep transmitting till high-time interrupt occurs.
Fcarrier
low time width high time width low time width high time width IR disable
HF IRE IROUT
start
Always high- level
Fig. 6-11c LGP=0, HF=1, When IRE goes Low from High, IROUT Pin Outputs Waveform
The following figure shows LGP=0 and HF=0. The IROUT waveform cannot modulate the Fcarrier waveform at low-time segments of the pulse. So IROUT waveform is determined by high time width and low time width. This mode can produce standard PWM waveform when IRE goes low from high. The output waveform of IROUT will keep on transmitting till high-time interrupt occurs.
Fcarrier
HF
low time width high time width low time width
start
high time width
IR disable
IRE IROUT
Always high-level
Fig. 6-11d LGP=0, HF=0, When IRE goes Low from High, Irout Pin Output Waveform
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 51
EM78P258N
8-Bit Microprocessor with OTP ROM The following figure shows LGP=1 and HF=1. When this bit is set to high level, the high-time segment of the pulse is ignored. So, IROUT waveform output is determined by low-time width.
Fcarrier
low time width
low time width
low time width
high time width
HF IRE IROUT
start
IR disable
Always high-level
Fig. 6-11e LGP=1 and HP=1, IROUT Pin Output Waveform
6.8.3
Programming the Related Registers
When defining IR/PWM, refer to the related registers of its operation as shown in the tables below. IR/PWM Related Control Registers
Address 0x09 0X0A 0x0F 0X0B Name IOC90 IR CR /IOCA0 IMR /IOCF0 HLTS /IOCB1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 IRE/0 Bit 2 Bit 1 Bit 0 TCCBHE TCCBEN/0 TCCBTS/0 TCCBTE/0 /0 TCCCSE TCCCS2/0 TCCCS1/0 TCCCS0/0 /0
TCCCEN/0TCCCTS/0 TCCCTE/0 HF/0 EXIE/0 LTS2/0 LGP/0 ICIE/0 LTS1/0 IROUTE/0 TCIE/0 LTS0/0
LPWTIE HPWTIE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0 /0 HTSE /0 HTS2/0 HTS1/0 HTS0/0 LTSE/0
IR/PWM Related Status/Data Registers
Address 0x0F 0x06 0X09 0X0A Name ISR/RF TCCC /IOC81 LTR /IOC91 HTR /IOCA1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXIF/0 Bit 1 ICIF/0 Bit 0 TCIF/0
LPWTIF/0 HPWTIF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0 LTR7/0 HTR7/0 LTR6/0 HTR6/0 LTR5/0 HTR5/0 LTR4/0 HTR4/0 LTR3/0 HTR3/0 LTR2/0 HTR2/0 LTR1/0 HTR1/0 LTR0/0 HTR0/0
52 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.9
Timer / Counter
6.9.1 Overview
TimerA (TCCA ) is an 8-bit clock counters. TimerB (TCCB) is a 16-bit clock counter. TimerC (TCCC) is an 8-bit clock counters that can be extended to 16-bit clock counter with programmable scalers. TCCA, TCCB, and TCCC can be read and written; and are cleared at every reset condition.
6.9.2 Function Description
Set predict value
TCCAEN
Set predict value
Set predict value
TCCBEN
TCCCEN
Set TCCAIF TCCA
Overflow
TCCB
Set TCCBIF
Set TCCCIF TCCC
Overflow
System clock
Overflow
8-to-1 MUX
TCCCS1 ~ TCCCS0
System clock or External input
8 Bit counter
System clock
Fig. 6.12 TIMER Block Diagram
Each signal and block of the above TIMER block diagram is described as follows: TCCX: Timer A~C register. TCCX increases until it matches with zero, and then reload the predicted value. When writing a value to TCCX, the predicted value and TCCX value become the set value. When reading from TCCX, the value will be the TCCX direct value. When TCCXEN is enabled, the reload of the predicted value to TCCX, TCCXIE is also enabled. TCCXIF will be set at the same time. It is an up counter. Under TCCA Counter (IOC51): IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on any reset condition and is an UP Counter.
NOTE TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)] TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2(CLK=4)]
Under TCCB Counter (IOC61): An 8-bit clock counter is for the least significant byte of TCCBX (TCCB). It can be read, written, and cleared on any reset condition and is an UP Counter.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 53
EM78P258N
8-Bit Microprocessor with OTP ROM Under TCCBH / MSB Counter (IOC71): An 8-bit clock counter is for the most significant byte of TCCBX (TCCBH). It can be read, written, and cleared on any reset condition. When TCCBHE (IOC90) is "0," then TCCBH is disabled. When TCCBHE is"1," then TCCB is a 16-bit length counter.
NOTE When TCCBH is Disabled: TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 1(CLK=2)] TCCB timeout period [1/Fosc x ( 256 - TCCB cnt ) x 2(CLK=4)] When TCCBH is Enabled: TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 1(CLK=2)} TCCB timeout period {1/Fosc x [ 65536 - (TCCBH * 256 + TCCB cnt)] x 2(CLK=4)}
Under TCCC Counter (IOC81): IOC81 (TCCC) is an 8-bit clock counter. It can be read, written, and cleared on any reset condition. If HF (Bit 2 of IOCA0) = 1 and IRE (Bit 3 of IOCA0) = 1, TCCC counter scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in Section 6.8.2, Function Description). Then TCCC value will be TCCC predict value. When HP = 0 or IRE = 0, the TCCC is an UP Counter.
NOTE Under TCCC UP Counter mode: TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 1(CLK=2)] TCCC timeout period [1/Fosc x scaler (IOCA0) x (256-TCCC cnt) x 2(CLK=4)]
When HP = 1 and IRE = 1, TCCC counter scale uses the low-time segments of the pulse generated by Fcarrier frequency modulation
NOTE Under IR mode: Fcarrier = FT/ 2 { [1+decimal TCCC Counter value (IOC81)] * TCCC Scale (IOCA0) } FT is system clock: FT = Fosc/1 (CLK=2) FT = Fosc/2 (CLK=4)
54 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
6.9.3 Programming the Related Registers
When defining TCCX, refer to the related registers of its operation as shown in the tables below. TCCX Related Control Registers:
Address 0x08 0x09 0x0A 0x0F Name IOC80 IOC90 IR CR /IOCA0 IMR /IOCF0 Bit 7 0 Bit 6 0 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 IRE/0 Bit 2 Bit 1 Bit 0
TCCAEN TCCATS TCCATE /0 /0 /0 TCCCEN /0 HF/0 EXIE/0 0 LGP/0 ICIE/0 0 IROUTE/0 TCIE/0
TCCBHE TCCBEN /0 /0
TCCCSE TCCCS2 TCCCS1/ TCCCS0 /0 /0 0 /0
LPWTE/0 HPWTE/0 TCCCIE/0 TCCBIE/0 TCCAIE/0
Related TCCX Status/Data Registers:
Address 0x0F 0x05 0x06 0x07 0x08 Name ISR/RF TCCA /IOC51 TCCB /IOC61 TCCBH /IOC71 TCCC /IOC81 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXIF/0 Bit 1 ICIF/0 Bit 0 TCIF/0
LPWTF/0 HPWTF/0 TCCCIF/0 TCCBIF/0 TCCAIF/0
TCCA7/0 TCCA6/0 TCCA5/0 TCCA4/0 TCCA3/0 TCCA2/0 TCCA1/0 TCCA0/0 TCCB7/0 TCCB6/0 TCCB5/0 TCCB4/0 TCCB3/0 TCCB2/0 TCCB1/0 TCCB0/0 TCCBH7 /0 TCCBH6 /0 TCCBH5 /0 TCCBH4 /0 TCCBH3 /0 TCCBH2 /0 TCCBH1 TCCBH0 /0 /0
TCCC7/0 TCCC6/0 TCCC5/0 TCCC4/0 TCCC3/0 TCCC2/0 TCCC1/0 TCCC0/0
6.10 Oscillator
6.10.1 Oscillator Modes
The EM78P258N can be operated in four different oscillator modes, such as High XTAL oscillator mode (HXT), Low XTAL oscillator mode (LXT), External RC oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator mode (IRC). You can select one of them by programming the OSC2, OCS1, and OSC0 in the CODE Option register.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 55
EM78P258N
8-Bit Microprocessor with OTP ROM The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below. Oscillator Modes
ERC (External RC oscillator mode); P70/OSCO acts as P70 ERC (External RC oscillator mode); P70/OSCO acts as OSCO IRC (Internal RC oscillator mode); P70/OSCO acts as P70 IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO LXT (Low XTAL oscillator mode) HXT High XTAL oscillator mode) (default)
1
OSC2
0 0 0 0 1 1
OSC1
0 0 1 1 1 1
OSC0
0 1 0 1 0 1
1 1
2 2
3
3
Under ERC mode, OSCI is used as oscillator pin. OSCO/P70 is defined by code option WORD0 Bit6 ~ Bit4. Under IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code option WORD0 Bit6 ~ Bit4. Under LXT and HXT modes; OSCI and OSCO are used as oscillator pins. These pins and cannot and should not be defined as normal I/O pins.
2
3
NOTE The transient point of system frequency between HXT and LXY is around 400 KHz.
The maximum operating frequency limit of crystal/resonator at different VDDs, are as follows:
Conditions VDD 2.3 Two clocks 3.0 5.0 Max. Freq. (MHz) 4 8 20
6.10.2 Crystal Oscillator/Ceramic Resonators (XTAL)
EM78P258N can be driven by an external clock signal through the OSCI pin as illustrated below.
OSCI EM78P258N OSCO
Fig. 6-13 External Clock Input Circuit
56 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM In the most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 6-14 below depicts such circuit. The same applies to the HXT mode and the LXT mode.
C1 OSCI EM78P258N
XTAL
OSCO RS C2
Fig. 6-14 Crystal/Resonator Circuit
The following table provides the recommended values for C1 and C2. Since each resonator has its own attribute, you should refer to the resonator specifications for appropriate values of C1 and C2. RS, a serial resistor, may be required for AT strip cut crystal or low frequency mode. Capacitor selection guide for crystal oscillator or ceramic resonators:
Oscillator Type Ceramic Resonators Frequency Mode HXT Frequency 455 kHz 2.0 MHz 4.0 MHz 32.768kHz LXT Crystal Oscillator HXT 100KHz 200KHz 455KHz 1.0MHz 2.0MHz 4.0MHz C1(pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 C2(pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15
Circuit diagrams for serial and parallel modes Crystal/Resonator:
330
C 7404
EM78P258N
330
OSCI
7404
7404
XTAL
Fig. 6-15 Serial Mode Crystal/Resonator Circuit Diagram
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 57
EM78P258N
8-Bit Microprocessor with OTP ROM
7404
4.7K
10K Vdd
O SC I
7404
EM 78P258N
10K
10K C1 C2
Fig. 6-16 Parallel Mode Crystal/Resonator Circuit Diagram
6.10.3 External RC Oscillator Mode
For some applications that do not require precise timing calculation, the RC oscillator (Fig. 6-17 right) could offer you with effective cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation.
Vcc Rext
OSCI EM78P258N
Cext
Fig. 6-17 External RC Oscillator Mode Circuit
In order to maintain a stable system frequency, the values of the Cext should be no less than 20pF, and that of Rext should be no greater than 1M. If the frequency cannot be kept within this range, the frequency can be affected easily by noise, humidity, and leakage. The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator will become unstable because the NMOS cannot discharge the capacitance current correctly. Based on the above reasons, it must be kept in mind that all supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the way the PCB is layout, have certain effect on the system frequency.
58 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM The RC Oscillator frequencies:
Cext Rext 3.3k 20 pF 5.1k 10k 100k 3.3k 100 pF 5.1k 10k 100k 3.3k 300 pF 5.1k 10k 100k Average Fosc 5V,25C 3.5 MHz 2.5 MHz 1.30 MHz 140 KHz 1.27 MHz 850 KHz 450 KHz 48 KHz 560 KHz 370 KHz 196 KHz 20 KHz Average Fosc 3V,25C 3.2 MHz 2.3 MHz 1.25 MHz 140 KHz 1.21 MHz 820 KHz 450 KHz 50 KHz 540 KHz 360 KHz 192 KHz 20 KHz NOTE: 1. Measured on DIP packages 2. Design reference only 3. The frequency drift is about 30%
6.10.4 Internal RC Oscillator Mode
EM78P258N offers a versatile internal RC mode with default frequency value of 4MHz. Internal RC oscillator mode has other frequencies (1MHz, 8MHz, and 455KHz) that can be set by CODE OPTION (WORD1), RCM1, and RCM0. Table below describes the EM78P258N internal RC drift with the variation of voltage, temperature, and process. Internal RC Drift Rate (Ta=25
Internal RC Frequency 4MHz 8MHz 1MHz 455MHz
, VDD=5V 5%, VSS=0V)
Drift Rate
Temperature (-40 ~+80 ) 10% 10% 10% 10%
Voltage (2.3V~5.5V) 5% 6% 5% 5%
Process 4% 4% 4% 4%
Total 19% 20% 19% 19%
Theoretical values, for reference only. Actual values may vary depending on actual process.
6.11 Power-on Considerations
Any microcontroller is not warranted to start operating properly before the power supply stabilizes in steady state. The EM78P258N POR voltage range is 1.9 ~ 2.1V. Under customer application, when power is switched OFF, Vdd must drop below 1.9V and remains at OFF state for 10s before power can be switched ON again. Subsequently, the EM78P258N will reset and work normally. The extra external reset circuit will work well if Vdd rises fast enough (50ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 59
EM78P258N
8-Bit Microprocessor with OTP ROM
6.11.1 Programmable WDT Time-Out Period
The Option word (WDTPS) is used to define the WDT time-out period (18ms5 or 4.5ms6). Theoretically, the range is from 4.5ms or 18ms. For most of crystal or ceramic resonators, the lower the operation frequency is, the longer is the required set-up time.
6.11.2 External Power-on Reset Circuit
The circuit shown in the following figure implements an external RC to produce a reset pulse. The pulse width (time constant) should be kept long enough to allow Vdd to reach the minimum operating voltage. This circuit is used when the power supply has a slow power rise time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be great than 40 K. This way, the voltage at Pin /RESET is held below 0.2V. The diode (D) acts as a short circuit at power-down. The "C" capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.
Vdd EM78P258N /RESET Rin C R D
Fig. 6-18 External Power on Reset Circuit
6.11.3 Residual Voltage Protection
When the battery is replaced, device power (Vdd) is removed but the residual voltage remains. The residual voltage may trips below Vdd minimum, but not to zero. This condition may cause a poor power on reset. Fig. 6-19 and Fig. 6-20 show how to create a protection circuit against residual voltage.
5
VDD=5V, WDT time-out period = 16.5ms 30%. VDD=3V, WDT time-out period = 18ms 30%. VDD=5V, WDT time-out period = 4.2ms 30%. VDD=3V, WDT time-out period = 4.5ms 30%. Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
6
60 *
EM78P258N
8-Bit Microprocessor with OTP ROM
Vdd EM78P258N Q1 /RESET 100K 1N4684 10K 33K
Vdd
Fig. 6-19 Residual Voltage Protection Circuit 1
Vdd
R1
Vdd
EM78P258N
Q1
/RESET
R3 R2
Fig. 6-20 Residual Voltage Protection Circuit 2
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 61
EM78P258N
8-Bit Microprocessor with OTP ROM
6.12 Code Option
EM78P258N has two CODE option words and one Customer ID word that are not a part of the normal program memory. Word 0
Bit12 ~ Bit0
Word1
Bit12 ~ Bit0
Word 2
Bit12 ~ Bit0
6.12.1 Code Option Register (Word 0)
WORD 0 Bit 12 Bit 11 Bit 10
- - -
Bit 9
TYP
Bit 8
Bit 7
Bit 6
Bit 5
OSC1
Bit 4
OSC0
Bit 3
HLP
Bit 2
PR2
Bit 1
PR1
Bit 0
PR0
CLKS ENWDTB OSC2
Bit 12 ~ 10: Bit 9 (TYPE):
Not used (reserved). These bits are set to "1" all the time Type selection. 1 = EM78P258N (default) The bit is set to "1" all the time
Bit 8 (CLKS):
Instruction period option bit 0 = two oscillator periods 1 = four oscillator periods (default) Refer to the Section 6.15 for Instruction Set
Bit 7 (ENWDTB):
Watchdog timer enable bit 0 = Enable 1 = Disable (default)
Bit 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Modes Selection bits Oscillator Modes
ERC (External RC oscillator mode); P70/OSCO acts as P70 ERC (External RC oscillator mode); P70/OSCO acts as OSCO IRC (Internal RC oscillator mode); P70/OSCO acts as P70 IRC (Internal RC oscillator mode); P70/OSCO acts as OSCO LXT (Low XTAL oscillator mode) HXT High XTAL oscillator mode) (default)
1
OSC2
0 0 0 0 1 1
OSC1
0 0 1 1 1 1
OSC0
0 1 0 1 0 1
1 1
2 2
3
3
Under ERC mode, OSCI is used as oscillator pin. OSCO/P70 is defined by code option WORD0 Bit6 ~ Bit4. Under IRC mode, P55 is normal I/O pin. OSCO/P70 is defined by code option WORD0 Bit6 ~ Bit4. Under LXT and HXT modes; OSCI and OSCO are used as oscillator pins. These pins and cannot and should not be defined as normal I/O pins.
2
3
NOTE The transient point of system frequency between HXT and LXY is around 400 KHz.
62 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 3 (HLP): Power consumption selection 0 = Low power consumption, applies to working frequency at or below 4MHz 1 = High power consumption, applies to working frequency above 4MHz Bit 2 ~ 0 (PR2 ~ PR0): Protect Bits PR2 ~ PR0 are protect bits. Each protect status is as follows: PR2
0 0 0 0 1 1 1 1
PR1
0 0 1 1 0 0 1 1
PR0
0 1 0 1 0 1 0 1
Protect
Enable Enable Enable Enable Enable Enable Enable Disable
6.12.2 Code Option Register (Word 1)
WORD 1 Bit 12 Bit 11 Bit 10
-
Bit 9
Bit 8
NRE
Bit 7
WDTPS
Bit 6
CYES
Bit 5
C3
Bit 4
C2
Bit 3
C1
Bit 2
C0
Bit 1
RCM1
Bit 0
RCM0
RCOUT NRHL
Bits 12 ~ 11: Bit 10 (RCOUT):
Not used (reserved). These bits are set to "1" all the time System clock output enable bit in IRC or ERC mode 0 = OSCO pin is open drain 1 = OSCO output system clock
Bit 9 (NRHL):
Noise rejection high/low pulses define bit. INT pin is falling edge trigger 0 = Pulses equal to 8/fc [s] is regarded as signal 1 = Pulses equal to 32/fc [s] is regarded as signal (default)
NOTE The noise rejection function is turned off under the LXT and sleep mode.
Bit 8 (NRE):
Noise rejection enable 0 = disable noise rejection 1 = enable noise rejection (default), but under Low XTAL oscillator (LXT) mode, the noise rejection circuit is always disabled.
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 63
EM78P258N
8-Bit Microprocessor with OTP ROM Bit 7 (WDTPS): WDT time-out Period Selection bit
WDT Time 1 0
WDT time-out Period *
18 ms 4.5 ms
*Theoretical values, for reference only Bit 6 (CYES): Instruction cycle selection bit 0 = one instruction cycle. 1 = two instructions cycle (default) Bit 5, 4, 3, & Bit 2 (C3, C2, C1, C0): Calibrator of internal RC mode C3, C2, C1, & C0 must be set to "1" only (auto-calibration). Bit 1 & Bit 0 (RCM1, RCM0): RC mode selection bits
RCM 1 1 1 0 0 RCM 0 1 0 1 0 Frequency (MHz) 4 8 1 455kHz
6.12.3 Customer ID Register (Word 2)
WORD 2 Bit 12 Bit 11 Bit 10
X X X
Bit 9
X
Bit 8
X
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Bit 12 ~ 0 : Customer's ID code
6.13 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case, these instructions need one or two instruction cycles as determined by Code Option Register CYES bit. In addition, the instruction set has the following features: 1. Every bit of any register can be set, cleared, or tested directly. 2. The I/O registers can be regarded as general registers. That is, the same instruction can operate on I/O registers.
64 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM The symbol "R" represents a register designator that specifies which one of the registers (including operational registers and general-purpose registers) is to be utilized by the instruction. The symbol "b" represents a bit field designator that selects the value for the bit located in the register "R" that is affected by the operation. The symbol "k" represents an 8 or 10-bit constant or literal value. The following are the EM78P258N instruction set Instruction Binary HEX Mnemonic
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0110 0110 0110 0110 0111 0111 0111 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0001 0001 01rr 1000 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 11rr 00rr 01rr 10rr 0000 0001 0010 0011 0100 rrrr 0000 0001 0010 0011 0100 rrrr rrrr 0000 rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R
Operation
No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R A VR A A VR R A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1),R(0) C, C A(7) R(n) R(n-1),R(0) C, C R(7) R(n) A(n+1),R(7) C, C A(0) R(n) R(n+1),R(7) C, C R(0) R(0-3) A(4-7),R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero
Status Affected
None C None T,P T,P 1 None None None None None None 1 None None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None None None * 65
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM Instruction Binary HEX Mnemonic
0 0 0 0 0 1 1 1 1 1 1 1 1 1 0111 100b 101b 110b 111b 00kk 01kk 1000 1001 1010 1011 1100 1101 1111 11rr bbrr bbrr bbrr bbrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk rrrr rrrr rrrr rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1Fkk
Operation
Status Affected
JZ R R+1 R, skip if zero None 2 BC R,b 0 R(b) None 3 BS R,b 1 R(b) None JBC R,b if R(b)=0, skip None JBS R,b if R(b)=1, skip None CALL k PC+1 [SP],(Page, k) PC None JMP k (Page, k) PC None MOV A,k kA None OR A,k AkA Z AND A,k A&kA Z XOR A,k AkA Z RETL k k A,[Top of Stack] PC None SUB A,k k-A A Z,C,DC ADD A,k k+A A Z,C,DC 1 This instruction is applicable to IOC50 ~ IOCF0, IOC51 ~ IOCC1 only. 2 This instruction is not recommended for RF operation. 3 This instruction cannot operate under RF.
7
Absolute Maximum Ratings
Items
Temperature under bias Storage temperature Input voltage Output voltage Working Voltage Working Frequency -40C -65C Vss-0.3V Vss-0.3V 2.5V DC
Rating
to to to to to to 85C 150C Vdd+0.5V Vdd+0.5V 5.5V 20MHz
66 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
8
DC Electrical Characteristics
(Ta=25 C, VDD=5.0V5%, VSS=0V)
Parameter XTAL: VDD to 5V Fxt XTAL: VDD to 3V ERC: VDD to 5V IRC: VDD to 5 V IRC:VDD to 5V IRC:VDD to 5V IRC:VDD to 5V IRC:VDD to 5V Input High Threshold Voltage (Schmitt trigger ) Input Low Threshold Voltage (Schmitt trigger ) Input Leakage Current for input pins Input High Voltage (Schmitt trigger ) Condition Two cycle with two clocks R: 5.1K, C: 100 pF 8MHz,4MHz, 1MHz, 455KHz RCM0:RCM1=1:1 RCM0:RCM1=1:0 RCM0:RCM1=0:1 RCM0:RCM1=0:0 OSCI in RC mode OSCI in RC mode VIN = VDD, VSS Ports 5, 6, 7 -1 Min DC DC F30% F30% 3.84 7.68 0.96 436.8 830 F 4.0 8.0 1.0 455 3.5 1.5 0 3.75 1.25 2.0 1.0 3.75 1.25 3.5 1.5 -3.7 -10 10 15 -50 25 -75 40 1.0 -240 120 2.0 15 15 20 35 1 Typ 8 F30% F30% 4.16 8.32 1.06 473.2 Max 20 Unit MHz MHz KHz Hz MHz MHz MHz KHz V V A V V V V V V V V mA mA mA mA A A A A A
Symbol
IRC1 IRC2 IRC3 IRC4 VIHRC VILRC IIL VIH1 VIL1 VIHT1 VILT1 VIHT2 VILT2 VIHX1 VILX1 IOH1 IOH2 IOL1 IOL2 IPH IPL ISB1 ISB2 ICC1
Input Low Voltage (Schmitt Ports 5, 6, 7 trigger ) Input High Threshold Voltage (Schmitt trigger ) Input Low Threshold Voltage (Schmitt trigger ) Input High Threshold Voltage (Schmitt trigger ) Input Low Threshold Voltage (Schmitt trigger ) Clock Input High Voltage Clock Input Low Voltage Output High Voltage (Ports 5, P60~66,P70) Output High Voltage (IR OUT (Port67)) Output Low Voltage (Ports 5, P60~66,P70) Output Low Voltage (IR OUT (Port67)) Pull-high current Pull-low current Power down current Power down current Operating supply current at two clocks(VDD to 3V) /RESET /RESET TCC,INT TCC,INT OSCI in crystal mode OSCI in crystal mode VOH = VDD-0.5V VOH = VDD-0.5V VOL = GND+0.5V VOL = GND+0.5V Pull-high active, input pin at VSS Pull-low active, input pin at Vdd All input and I/O pins at VDD, outpu pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled /RESET= 'High', Fosc=32KHz (Crystal type,CLKS="0"), output pin floating, WDT disabled
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 67
EM78P258N
8-Bit Microprocessor with OTP ROM
/RESET= 'High', Fosc=32KHz (Crystal type,CLKS="0"), output pin floating, WDT enabled /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled /RESET= 'High', Fosc=10MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled
ICC2
Operating supply current at two clocks (VDD to 3V) Operating supply current at two clocks Operating supply current at two clocks
25
35
A
ICC3
1.9
2.2
mA
ICC4
3.0
3.5
mA
NOTE:
1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical results at 25 . These data are for design guidance only.
8.1
Symbol VAREF VASS VAI IAI1 Ivdd Ivref Ivdd IVref
AD Converter Characteristics
(Vdd=2.5V to 5.5V, Vss=0V, Ta=25
Parameter Analog reference voltage Analog input voltage Analog supply current
)
Min. 2.5 Vss VASS 750 -10 500 200 450 10 0 0 0 0 0 4 15 0 0 4.7 0.1 0 Typ. - - - 850 0 600 250 550 11 4 0.5 4 2 8 - - - 0.2 4.8 0.3 - Max. Vdd Vss VAREF 1000 +10 820 300 650 - 8 0.9 8 4 10 - 15 VAREF 0.3 5 - 2 Unit V V V uA uA uA uA uA Bits LSB LSB LSB LSB K us TAD V V V/us LSB
Condition VAREF - VASS 2.5V - Vdd=VAREF=5.0V, VASS =0.0V(V reference from Vdd) Vdd=VAREF=5.0V, VASS=0.0V (V reference from VREF) Vdd=5.0V, OP used Output voltage swing 0.2V to 4.8V Vdd=VAREF=5.0V, VASS =0.0V Vdd = 2.5 to 5.5V Ta=25 Vdd = 2.5 to 5.5V Ta=25 Vdd=VAREF=5.0V, VASS =0.0V Vdd=VAREF=5.0V, VASS =0.0V - Vdd=VAREF=5.0V, VASS =0.0V Vdd=VAREF=5.0V, VASS =0.0V Vdd=VAREF=5.0V, VASS =0.0V Vdd=VAREF=5.0V, VASS =0.0V,RL=10K Vdd=VAREF=5.0V, VASS =0.0V Vdd=5.0V0.5V
IAI2
Analog supply current
IOP RN LN DNL FSE OE ZAI TAD TCN ADIV ADOV ADSR PSR NOTE:
OP current Resolution Linearity error Differential nonlinear error Full scale error Offset error Recommended impedance of analog voltage source ADC clock period AD conversion time ADC OP input voltage range ADC OP output voltage swing ADC OP slew rate Power Supply Rejection
1. These parameters are hypothetical (not tested) and are provided for design reference use only. 2. There is no current consumption when ADC is off other than minor leakage current. 3. AD conversion result will not decrease when the increase of input voltage and no missing code will result. Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
68 *
EM78P258N
8-Bit Microprocessor with OTP ROM
8.2
Device Characteristics
The graphs provided following note that based on a limited number of samples and they are provided for information only. The device characteristic listed herein is not guaranteed. In the graphs, the data maybe out of the specified operating warranted range.
IRC OSC Frequency (VDD=3V)
Frequency (M Hz)
Temperature (
)
Fig. 8-1 Internal RC OSC Frequency vs. Temperature, VDD=3V
Fig. 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 69
EM78P258N
8-Bit Microprocessor with OTP ROM
9
AC Electrical Characteristic
(Ta=25 C, VDD=5V5%, VSS=0V)
Symbol Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time ERC delay time Cload=20pF Ta = 25C 15 45 1 Ta = 25C Ta = 25C Ta = 25C Crystal type RC type Conditions Min 45 100 500 (Tins+20)/N* 11.3 2000 11.3 16.2 0 20 50 3 25 55 5 21.6 16.2 21.6 Typ 50 Max 55 DC DC Unit % ns ns ns ms ns ms ns ns ns ns
Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Tdrc NOTE:
1. N = selected prescaler ratio 2. Twdt1: The Option word1 (WDTPS) is used to define the oscillator set-up time. WDT timeout length is the same as set-up time (18ms). 3. Twdt2: The Option word1 (WDTPS) is used to define the oscillator set-up time. WDT timeout length is the same as set-up time (4.5ms). 4. These parameters are hypothetical (not tested) and are provided for design reference only. 5. Data under minimum, typical, & maximum (Min, Typ, & Max) columns are based on hypothetical results at 25 . These data are for design reference use only. 6. The Watchdog timer duration is determined by code option Word1 (WDTPS).
70 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
10 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V
0.75VDD 0.25VDD
TEST POINTS
0.75VDD 0.25VDD
GND+0.5V
AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins CLK
TCC
Ttcc
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 71
EM78P258N
8-Bit Microprocessor with OTP ROM
APPENDIX A. Package Types Summary
OTP MCU EM78P258NP EM78P258NN Package Type DIP SOP Pin Count 14 14 Package Size 300mil 150mil
B Packaging Configurations
B.1 14-Lead Plastic Dual in line (PDIP) 300 mil
72 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
B.2 14-Lead Plastic Small Outline (SOP)
150 mil
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 73
EM78P258N
8-Bit Microprocessor with OTP ROM
C Quality Assurance and Reliability
Test category Solderability Test conditions Solder temperature=2455 , for 5 seconds up to the stopper using a rosin-type flux Step 1: TCT, 65 (15mins)~150 (15mins), 10 cycles Remarks
Step 2: Bake at 125 , TD (endurance)=24 hrs Step 3: Soak at 30C/60% TD (endurance)=192 hrs Pre-condition Step 4: IR flow 3 cycles (Pkg thickness 2.5mm or Pkg volume 350mm3 ----2255 ) (Pkg thickness 2.5mm or Pkg volume 350mm3 ----2405 Temperature cycle test Pressure cooker test High temperature / High humidity test High-temperature storage life High-temperature operating life Latch-up ESD (HBM) -65 (15mins)~150 (15mins), 200 cycles ) For SMD IC (such as SOP, QFP, SOJ, etc)
TA =121 , RH=100%, pressure=2 atm, TD (endurance)= 96 hrs TA=85 , RH=85% TD (endurance)=168 , 500 hrs
TA=150 , TD (endurance)=500, 1000 hrs TA=125 , VCC=Max. operating voltage, TD (endurance) =168, 500, 1000 hrs TA=25 , VCC=Max. operating voltage, 150mA/20V IP_ND,OP_ND,IO_ND TA=25 , 3KV IP_NS,OP_NS,IO_NS IP_PD,OP_PD,IO_PD, IP_PS,OP_PS,IO_PS,
ESD (MM)
TA=25 ,
300V
VDD-VSS(+),VDD_VSS (-)mode
C.1 Address Trap Detect
An address trap detect is one of the MCU embedded fail-safe functions that detects MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction from a certain section of ROM, an internal recovery circuit is auto started. If a noise caused address error is detected, the MCU will repeat execution of the program until the noise is eliminated. The MCU will then continue to execute the next program.
74 *
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
EM78P258N
8-Bit Microprocessor with OTP ROM
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
* 75

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